US 9,871,063 B1Granted

Display driver semiconductor device and manufacturing method thereof

AssigneeMagnaChip Semiconductor, Ltd.

InventorsBo Seok Oh, Hee Hwan Ji, Jeong Hyeon Park

Life of this patent

Estimating the term…

Loading patent…

Abstract

A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.

Claims20

Dependent claims

A method for manufacturing a display driver semiconductor device, comprising:

forming a plurality of trench isolating regions on a substrate defining a first region, a second region, and a third region;
forming a high voltage well region on the substrate;
forming a pair of low-concentration drift regions inside the high voltage well region on the second and third regions, respectively;
forming a low voltage well region inside the high voltage well region on the first region;
depositing a chemical vapor deposition (CVD) insulating layer through the first, second, and third regions of the substrate;
patterning the CVD insulating layer to remove the CVD insulating layer on the first region and the second region;
forming a first thermal oxide layer, a second thermal oxide layer, and a third thermal oxide layer on the first, second, and the third regions, respectively;
removing the first thermal oxide layer by patterning and respectively forming a second gate insulating layer and a third gate insulating layer on the second and the third regions;
forming a first gate insulating layer on the first region by forming the second thermal oxide layer on the first region;
and
forming a first gate electrode, a second gate electrode, and a third gate electrode on the first, second, and the third regions, respectively, by depositing and patterning a conductive material on the substrate.

8 more elements

A display driver semiconductor device, comprising:

a low voltage semiconductor device, comprising:
a first gate insulating layer having a first thickness;
a high-concentration first source region and a high-concentration first drain region;
a pair of LDD regions having a shallower depth than depths of a first source doping region and a first drain doping region;
and
a first gate electrode;
a half voltage semiconductor device formed adjacent to the low voltage semiconductor device, comprising:
a second gate insulating layer having a second thickness;
a high-concentration second source and a high-concentration second drain region;
a pair of drift regions covering the high-concentration second source region and the high-concentration second drain region, respectively;
and
a second gate electrode;
and
a high voltage semiconductor device formed on a semiconductor substrate adjacent to the half voltage semiconductor device, the high voltage semiconductor device comprising:
a third gate insulating layer having a third thickness, the third gate insulating layer comprising a first insulating layer and a second insulating layer, the first insulating layer being a chemical vapor deposition (CVD) insulating layer and the second insulating layer being a thermal oxide layer;
a high-concentration third source region and a high-concentration third drain region;
a pair of drift regions covering the high-concentration third source region and the high-concentration third drain region, respectively;
and
a third gate electrode.

16 more elements

A display driver semiconductor device, comprising:

a high voltage well region being formed on a substrate;
a first semiconductor device formed on the high voltage well region, the first semiconductor device comprising:
a first gate insulating layer having a first thickness;
a first source region and a first drain region disposed on opposite sides below the first gate insulating layer;
a pair of LDD regions, each LLD region being respectively partially disposed between the first source region and the first drain region;
and
a first gate electrode disposed above the first gate insulating layer;
a second semiconductor device formed adjacent to the first semiconductor device, the second semiconductor device comprising:
a second gate insulating layer having a second thickness;
a high-concentration second source and a high-concentration second drain region disposed on opposite sides below the second gate insulating layer;
a pair of drift regions disposed on opposite sides to cover the high-concentration second source region and the high-concentration second drain region, respectively;
and
a second gate electrode disposed above the second gate insulating layer;
and
a third semiconductor device formed adjacent to the second semiconductor device, the third semiconductor device comprising:
a third gate insulating layer having a third thickness;
a high-concentration third source region and a high-concentration third drain region disposed on opposite sides below the third gate insulating layer;
a pair of drift regions disposed on opposite sides to cover the high-concentration third source region and the high-concentration third drain region, respectively;
and
a third gate electrode disposed above the third gate insulating layer,
wherein the third thickness has a size different than sizes of the first thickness and the second thickness.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/450,083Filed 6 Mar 2017
Priority: KR 10-2016-009015215 Jul 2016
Published: US 2018/0019262 A118 Jan 2018
Granted: 16 Jan 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
G11C 19/00
Digital stores in which the information is moved stepwise
H03K 19/017509
Coupling arrangements; Interface arrangements: interface arrangements
H10D 30/0213
Using self-aligned silicidation: providing different silicide thicknesses on gate electrodes and on source regions or drain regions