Enhanced charge storage materials, related semiconductor memory cells and semiconductor devices, and related systems and methods

A semiconductor device, comprising

• a memory array including volatile memory cells, at least one volatile memory cell of the volatile memory cells comprising:
• a gate electrode adjacent to a source region and a drain region within a substrate;
• and
• a capacitor coupled to one of the source region and the drain region, the capacitor configured to store a charge corresponding to logic states of the memory cell, the capacitor comprising:
• a top electrode;
• a bottom electrode;
• and
• a charge storage material configured and formulated to transition from a first phase exhibiting dielectric properties to a second phase exhibiting antiferroelectric properties responsive to exposure to an electric field during use and operation of the semiconductor device, the second phase exhibiting a higher capacitance than the first phase, wherein the charge storage material exhibits a nonlinear capacitance as a function of voltage at a voltage between about −0.8 V and about 0.8 V.

A method of operating a memory cell, the method comprising:

• providing a capacitor comprising a crystalline charge storage material comprising an oxide of zirconium, hafnium, and at least one element selected from the group consisting of bismuth, antimony, arsenic, titanium, niobium, aluminum, tantalum, strontium, and lanthanum, wherein the crystalline charge storage material exhibits hysteresis responsive to exposure to one of a positive voltage and a negative voltage and does not exhibit hysteresis responsive to exposure to the other of the positive voltage and the negative voltage;
• responsive to application of a voltage to the capacitor, transitioning the crystalline charge storage material from a first phase to a second phase that is relatively less stable than the first phase and exhibiting a higher capacitance than a capacitance of the first phase to store a charge on the capacitor;
• accessing the capacitor with an access line coupled to one of a source region or a drain region of the memory cell;
• and
• responsive to removing the voltage from the capacitor, transitioning the crystalline charge storage material from the second phase that is relatively less stable than the first phase to the first phase.

A system comprising:

• a semiconductor device comprising an array of memory cells, each memory cell of the array of memory cells comprising:
• a source region and a drain region within a substrate;
• a capacitor coupled to one of the source region and the drain region, the capacitor including a charge storage material having a crystal structure comprising an oxide of zirconium and at least another element, the charge storage material configured and formulated to transition from a first phase to a second phase when exposed to a voltage sufficient to store a charge on the memory cell, the second phase exhibiting a higher capacitance than the first phase, wherein the charge storage material exhibits substantially no change in polarization responsive to exposure to a voltage having a magnitude less than about 0.5 V and exhibits an increase in polarization responsive to exposure to a voltage greater than about 0.5 V;
• and
• a digit line electrically coupled to an electrode of the capacitor.