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US 9,871,043 B2Granted
4F2 SCR memory device
AssigneeHGST, Inc.
InventorDaniel R. Shepard
Life of this patent
Estimating the term…
Abstract
A memory-array is disclosed in which an array of threshold switching devices is constructed having an area per transistor of 2F2. This array of threshold switching devices is suitable for a variety of memory or other applications including PRAM, MRAM, RRAM, FRAM, OPT-RAM and 3-D memory.
Claims19
A memory device comprising an array of bipolar junction transistor devices whereby at least one of the gate connections to the bipolar junction devices is manufactured by growing silicon laterally in a trench;
- a plurality of bit lines that are parallel to one another;
- and
- a plurality of word lines that are parallel to one another, wherein each bit line is coupled to a plurality of information storage elements and each word line is coupled to the plurality of information storage elements wherein each information storage element is coupled to a respective input, a positive voltage supply and to ground.
A memory array, comprising:
- a plurality of threshold switching devices is constructed having an area per transistor of 2F2 wherein the switching devices are bipolar junction transistors.
A memory array, comprising:
- a plurality of bipolar junction transmitters is constructed having an area per transistor of 2F2 a plurality of bit lines that are parallel to one another;
- and
- a plurality of word lines that are parallel to one another, wherein the pluralities of bit lines are orthogonal to the plurality of word lines wherein each bit line is coupled to a plurality of information storage elements wherein each word line is coupled to a plurality of information storage elements wherein each information storage element is coupled to a respective input wherein each information storage element is additionally coupled to a positive voltage supply wherein each information storage element is additionally coupled to ground.
Dependencies are inferred from the claim text.