Resistance mitigation in physical design
AssigneeArm Limited
InventorsJean-Luc Pelloie, Marlin Wayne Frederick, Jr.
Life of this patent
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Abstract
Various implementations described herein are directed to an integrated circuit with mitigated resistance. The integrated circuit may include a cell having a plurality of transistors including a first transistor of a first type and a second transistor of a second type that is different from the first type. The integrated circuit may include a first wire coupling the first transistor to the second transistor. The integrated circuit may include a second wire coupling the first wire to an output routing wire. The integrated circuit may include a redundant wire further coupling the first wire to the output routing wire.
Claims13
An integrated circuit, comprising:
- a cell having a plurality of transistors including a first transistor of a first type and a second transistor of a second type that is different from the first type;
- a first wire coupling the first transistor to the second transistor, wherein the first wire is disposed in a first metal layer;
- and
- a plurality of wires coupling the first wire to an output routing wire, wherein the plurality of wires includes:
- a second wire coupling the first wire to the output routing wire, wherein the second wire is disposed in a second metal layer that is different than the first metal layer;
- and
- a redundant wire further coupling the first wire to the output routing wire, wherein the redundant wire is disposed in a third metal layer that is different than the first and second metal layers.
Dependencies are inferred from the claim text.