Semiconductor device and an electronic apparatus

An electronic device, comprising:

• a P-type substrate;
• an N-well in the P-type substrate;
• a first N+ diffusion region in the P-type substrate;
• a first P+ diffusion region in the N-well;
• a second P+ diffusion region located across a boundary between the P-type substrate and the N-well;
• a third P+ diffusion region in the P-type substrate;
• a first gate electrode overlying the N-well between the first P+ diffusion regions and the second P+ diffusion region;
• a second gate electrode overlying the P-type substrate between the second P+ diffusion region and the first N+ diffusion region and connected to the third P+ diffusion region, and both being connected to a ground pad;
• wherein the first P+ diffusion region, the N-well, the P-type substrate, and the first N+ diffusion region form an SCR (Silicon-Controlled rectifier) device;
• wherein the first P+ diffusion region, the second P+ diffusion region, and the first gate electrode form a PMOS structure;
• wherein the second P+ diffusion region, the first N+ diffusion region, and the second gate electrode form a gated diode structure;
• and
• wherein the first gate electrode, the first P+ diffusion region, and the second N+ diffusion region are coupled to an input/output (TO) pad.

An electronic apparatus, comprising a semiconductor device and an electronic assembly connected to said semiconductor device, wherein the semiconductor device comprises:

• a P-type substrate;
• an N-well in the P-type substrate;
• a first N+ diffusion region in the P-type substrate;
• a first P+ diffusion region in the N-well;
• a second P+ diffusion region located across a boundary between the P-type substrate and the N-well;
• a third P+ diffusion region in the P-type substrate;
• a first gate electrode overlying the N-well between the first P+ diffusion region and the second P+ diffusion region;
• a second gate electrode overlying the P-type substrate between the second P+ diffusion region and the first N+ diffusion region and connected to the third P+ diffusion region, and both being connected to a ground pad;
• wherein the first P+ diffusion region, the N-well, the P-type substrate, and the first N+ diffusion region form an SCR (Silicon-Controlled rectifier) device;
• wherein the first P+ diffusion region, the second P+ diffusion region, and the first gate electrode form a PMOS structure;
• wherein the second P+ diffusion region, the first N+ diffusion region, and the second gate electrode form a gated diode structure;
• and
• wherein the first gate electrode, the first P+ diffusion region, and the second N+ diffusion region are coupled to an input/output (IO) pad.