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US 9,871,020 B1Granted
Through silicon via sharing in a 3D integrated circuit
AssigneeGlobalfoundries Inc.
InventorsSebastian T. Ventrone, Sudeep Mandal
Life of this patent
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Abstract
The present disclosure generally relates to semiconductor structures and, more particularly, to intelligent through silicon via sharing in 3D-IC integrated structures and methods of manufacture. The structure includes: a plurality of stacked dies each containing at least one macro device; and a layer structure positioned between the plurality of stacked dies which comprises a control structured to route signals between the at least one macro device of a first stacked die and the at least one macro device of a second stacked die of the plurality of stacked dies.
Claims13
A structure comprising:
- a plurality of stacked dies each containing at least one macro device;
- and
- a layer structure positioned between the plurality of stacked dies which comprises a control structured to route signals between the at least one macro device of a first stacked die and the at least one macro device of a second stacked die of the plurality of stacked dies, wherein the control includes a control logic to selectively and dynamically route signals through a through silicon via (TSV) allocation which connects to the at least one macro device of a first die and a second die of the plurality of stacked dies, wherein
- the control comprises at least one multiplexer and at least one demultiplexer which forward the signals throughout the layer structure,
- the control logic selectively enables and disables the at least one multiplexer and the at least one demultiplexer to dynamically route the signals through the TSV allocation,
- the control logic selectively routes the signals through different TSV allocations,
- the control logic includes at least one of history tables, priority queues, programmed priority, and controller application,
- the layer structure further comprises a content addressable memory (CAM) which stores the history tables, and
- the history tables keep an accounting of requests from the at least one macro device to determine a frequency of the request.
6 more elements
A structure comprising:
- a plurality of dies each containing at least one macro device;
- and
- an interposer positioned between the plurality of dies which comprises a control block and a control logic to route signals between the at least one macro device of a first die and the at least one macro device of a second die of the plurality of dies and at least one multiplexer and at least one demultiplexer which route the signals between the plurality of dies, wherein the control logic selectively enables and disables the at least one multiplexer and the at least one demultiplexer to dynamically route signals through a plurality of through silicon vias (TSVs) between the plurality of dies, wherein
- the control comprises at least one multiplexer and at least one demultiplexer which forward the signals throughout the layer structure,
- the control logic selectively enables and disables the at least one multiplexer and the at least one demultiplexer to dynamically route the signals through the TSV allocation,
- the control logic selectively routes the signals through different TSV allocations,
- the control logic includes at least one of history tables, priority queues, programmed priority, and controller application,
- the layer structure further comprises a content addressable memory (CAM) which stores the history tables, and
- the history tables keep an accounting of requests from the at least one macro device to determine a frequency of the request.
6 more elements
A structure comprising:
- a plurality of stacked dies each containing at least one circuit;
- a layer structure positioned between the plurality of stacked dies which comprises a control block and a control logic to route signals between the at least one circuit of a first stacked die and the at least one circuit of a second stacked die of the plurality of stacked dies;
- and
- a plurality of through silicon vias (TSVs) selectively activated by and extending from the layer structure and connected to the least one circuit of the first die and to the least one circuit device of the second die, wherein
- the control block comprises at least one multiplexer and at least one demultiplexer which forward the signals throughout the layer structure,
- the control logic selectively enables and disables the at least one multiplexer and the at least one demultiplexer to dynamically route the signals through the TSV allocation,
- the control logic selectively routes the signals through different TSV allocations,
- the control logic includes at least one of history tables, priority queues, programmed priority, and controller application,
- the layer structure further comprises a content addressable memory (CAM) which stores the history tables, and
- the history tables keep an accounting of requests from the at least one macro device to determine a frequency of the request.
7 more elements
Dependencies are inferred from the claim text.