Multi-level chip interconnect
AssigneeInfineon Technologies AG
InventorsPeter Ossimitz, Tobias Jacobs
Life of this patent
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Abstract
Representative implementations of devices and techniques provide optimized electrical performance of interconnectivity components of multi-layer integrated circuits (IC) such as chip dice, for example. Different layers of the multi-layer IC include contact terminals that may be used to connect to circuits, systems, and carriers external to the IC.
Claims32
A multi-layered integrated circuit (IC), comprising:
- a first conductive layer comprising a first material;
- a first contact terminal coupled to the first conductive layer;
- a second conductive layer disposed over the first conductive layer, the second conductive layer comprising a second material;
- a second contact terminal coupled to the second conductive layer;
- at least one opening in the second conductive layer, the first contact terminal externally accessible via the at least one opening in the second conductive layer, such that the first contact terminal and the second contact terminal are concurrently externally accessible;
- and
- a protective covering enclosing the first and second conductive layers and including one or more openings in the protective covering for electrical access to at least one of the first and second contact terminals.
A multi-layered integrated circuit (IC), comprising:
- a first layer comprising copper traces;
- at least one copper contact terminal coupled to the first layer;
- a second layer comprising aluminum-alloy traces, disposed over the first layer;
- at least one aluminum-alloy contact terminal coupled to the second layer;
- and
- at least one opening in the second layer, a copper contact terminal coupled to the first layer protruding through the at least one opening in the second layer without making contact with the second layer, the copper contact terminal and the aluminum-alloy contact terminal arranged to be concurrently electrically coupled to one or more circuits external to the IC.
A multi-layered chip die, comprising:
- a plurality of metallic layers arranged in a stack, and including electrical contact nodes;
- a top level disposed over the stack, and having multiple terminal pads for electrically coupling the chip die to an external system;
- and
- multiple interconnects electrically coupling the electrical contact nodes of respective layers of the plurality of metallic layers to individual terminal pads at the top level, without making contact with other layers of the plurality of metallic layers of the chip die.
A multi-layered integrated circuit (IC), comprising:
- a first conductive layer comprising a first material;
- a first contact terminal coupled to the first conductive layer;
- a second conductive layer disposed over the first conductive layer, the second conductive layer comprising a second material;
- a second contact terminal coupled to the second conductive layer;
- and
- at least one opening in the second conductive layer, the first contact terminal externally accessible via the at least one opening in the second conductive layer, such that the first contact terminal and the second contact terminal are concurrently externally accessible, wherein the first contact terminal protrudes through the at least one opening in the second conductive layer without making contact to the second conductive layer.
A multi-layered integrated circuit (IC), comprising:
- a first conductive layer comprising a first material;
- a first contact terminal coupled to the first conductive layer;
- a second conductive layer disposed over the first conductive layer, the second conductive layer comprising a second material;
- a second contact terminal coupled to the second conductive layer;
- and
- at least one opening in the second conductive layer, the first contact terminal externally accessible via the at least one opening in the second conductive layer, such that the first contact terminal and the second contact terminal are concurrently externally accessible, wherein the first material is different than the second material.
A method, comprising:
- arranging a second conductive layer of a multi-layered integrated circuit (IC) over a first conductive layer of the IC;
- forming an opening in the second conductive layer;
- forming a first contact terminal to the first conductive layer, the first contact terminal externally accessible via the opening in the second conductive layer;
- forming a second contact terminal to the second conductive layer, the first contact terminal and the second contact terminal being concurrently externally accessible;
- and
- forming a protective covering enclosing the first and second conductive layers and including one or more openings in the protective covering for electrical access to at least one of the first and second contact terminals.
Dependencies are inferred from the claim text.