Wafer level package and fabrication method
AssigneeAmkor Technology, Inc.
InventorsRonald Patrick Huemoeller, Sukianto Rusli, David Razu
Life of this patent
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Abstract
A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.
Claims20
A method of making an electronic component package, the method comprising:
- coupling a bottom side of a semiconductor die to a top side of a substrate structure;
- covering at least lateral sides of the semiconductor die with an encapsulating material, wherein a bottom surface of the encapsulating material is lower than the bottom side of the semiconductor die;
- after said coupling and said covering, forming a via hole straight through at least a first dielectric layer and a second dielectric layer of the substrate structure to expose a conductive pad, where the first and second dielectric layers are directly coupled to each other with no intervening conductive material between them;
- and
- forming conductive material in the via hole.
A method of making an electronic component package, the method comprising:
- coupling a bottom side of each of a plurality of semiconductor dies to a top side of a substrate wafer in a two-dimensional array;
- forming a via hole straight through at least a first dielectric layer and a second dielectric layer of the substrate wafer, where the first and second dielectric layers are directly coupled to each other with no intervening conductive material between them;
- forming encapsulating material covering at least lateral sides of the semiconductor dies;
- forming conductive material in the via hole;
- forming conductive interconnection structures on a bottom side of the substrate wafer;
- and
- after said forming conductive interconnection structures, singulating the electronic component package from the substrate wafer by, at least in part, cutting through the encapsulating material, the first dielectric layer and the second dielectric layer.
An electronic component package comprising:
- a semiconductor die;
- an encapsulating material, wherein a bottom surface of the encapsulating material is lower than the bottom side of the semiconductor die;
- and
- a substrate structure comprising:
- a top side to which a bottom side of the semiconductor die is coupled;
- a first dielectric layer;
- a second dielectric layer directly on the first dielectric layer with no conductive material between the first and second dielectric layers;
- a via hole extending vertically through both the first and second dielectric layers;
- and
- conductive material in the via hole.
Dependencies are inferred from the claim text.