# US 9,871,007 B2 · Packaged integrated circuit device with cantilever structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,871,007 B2
- Document ID: US9871007B2
- Status: Granted
- Kind: B2
- Application number: 14/866,576
- Filed: 2015-09-25
- Published: 2017-03-30
- Granted: 2018-01-16
- Earliest claimed: 2015-09-25
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: John G. Meyers; Bilal Khalaf; Sireesha Gogineni; Brian J. Long
- Web page: https://patentgrep.com/patent/US9871007B2

## CPC

- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 70/68: Shapes or dispositions thereof
- H10W 72/071: {Connecting or disconnecting}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 90/00: Package configurations
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 44/248: {for antennas}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/10: characterised by their shape or disposition
- H10W 90/20: Configurations of stacked chips
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/284: {characterised by structural arrangements for measuring or testing}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device.

## Claims

### Claim 1

A device comprising:
a first package including a first package material and one or more integrated circuit (IC) dies disposed in the first package material, wherein an exterior of the first package material forms a first side, a second side opposite the first side, and a sidewall extending between a first edge of the first side and a second edge of the second side;
a first substrate coupled to the exterior of the first package material at the first side, wherein one of the first side and the second side is offset from a line extending from a first cantilever portion of the first substrate in a direction perpendicular to the first side, wherein the one or more IC dies are electrically coupled to the first substrate via the first side;
circuitry disposed on the first substrate, wherein the one or more IC dies are electrically coupled to the circuitry via the first substrate, the circuitry including a circuit structure disposed on the first cantilever portion;
a second substrate coupled to the exterior of the first package material at the second side, wherein the one or more IC dies are electrically coupled via the second substrate to a hardware interface at a surface of the second substrate;
a circuit component mounted onto the second substrate at a region of the second substrate which is outside of the first package, the circuit component electrically coupled to the one or more IC dies via the second substrate; and
a second package material disposed around each of the first package, the first substrate, the circuit structure and the circuit component, wherein the second package material adjoins the second substrate, wherein one or more interconnects, disposed in the second package material, provide electrical connection between the one or more IC dies and the second substrate.

### Claim 2 (depends on 1)

The device of claim 1, wherein only one of the first side and the second side is offset from the line.

### Claim 3 (depends on 1)

The device of claim 1, wherein the circuit structure is an interface contact.

### Claim 4 (depends on 3)

The device of claim 3, wherein the interface contact is configured to exchange one or more signals to test the one or more IC dies.

### Claim 5 (depends on 1)

The device of claim 1, wherein the circuit structure is disposed on a side of the first cantilever portion that faces toward the second substrate.

### Claim 6 (depends on 5)

The device of claim 5, further comprising: another circuit structure disposed on a side of the first cantilever portion that faces away from the second substrate.

### Claim 7 (depends on 1)

The device of claim 1, wherein the first substrate forms a second cantilever portion that extends past an edge of the first package.

### Claim 8 (depends on 7)

The device of claim 7, wherein the first cantilever portion and the second cantilever portion both extend past the edge of the first package.

### Claim 9 (depends on 8)

The device of claim 8, wherein the circuit component extends between the first cantilever portion and the second cantilever portion at a plane in which the first substrate extends.