US 9,870,966 B1Granted

Process for making semiconductor dies, chips and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of AACNT-TS via opens

AssigneePDF Solutions, Inc.

InventorsStephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama

Life of this patent

Estimating the term…

patentgrep

Loading patent…

Abstract

Improved processes for manufacturing semiconductor wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, and/or excessive resistance failure modes. Such processes include evaluating one or more Designs of Experiments (“DOEs”), each comprised of multiple NCEM-enabled fill cells, in at least two variants, targeted to the same failure mode. Such DOEs include multiple means/steps for enabling non-contact (NC) detection of AACNT-TS via opens.

Claims14

Dependent claims

A method for making integrated circuits (ICs), comprising at least:

(a) performing initial processing steps to produce a test wafer that includes a first Design of Experiments (DOE) of Non-Contact Electrical Measurement (NCEM)-enabled, source/drain contact (AACNT)-source/drain silicide (TS)-via-open-configured fill cells, said initial processing steps including:
(i) patterning, on the test wafer, a first means for enabling NC detection of AACNT-TS via opens;
and,
(ii) patterning, on the test wafer, a second means for enabling NC detection of AACNT-TS via opens;
wherein the first and second means for enabling NC detection of AACNT-TS via opens are different;
(b) determining a presence or absence of AACNT-TS via opens on the test wafer by:
performing a voltage contrast examination of NCEM-enabled fill cells in the first DOE, including at least the first and second means for enabling NC detection of AACNT-TS via opens;
and,
(c) using the results from step (b) to select NCEM-enabled fill cells for inclusion on a subsequent product wafer.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/281,508Filed 30 Sep 2016 · continuation
Priority: 16 Dec 2015
Granted: 16 Jan 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification27 codes

H10P 74/238
Characterised by multiple measurements, corrections, marking or sorting processes: comprising acting in response to an ongoing measurement without…
G01R 31/2884
Testing of integrated circuits [IC]: using dedicated test connectors, test elements or test circuits on the IC under test
G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
H10D 62/115
Isolations within a component, i.e. internal isolations: dielectric isolations, e.g. air gaps

Family

Application62/268,463Us provisional application · filed 16 Dec 2015
Application15/090,256Parent of this continuation · filed 4 Apr 2016
Application15/090,267Parent of this continuation · filed 4 Apr 2016
Application15/090,274Parent of this continuation · filed 4 Apr 2016
US 10,593,604 B1Related patent
US 2017/0178981 A1Published application
US 9,799,575 B2Related patent
US 9,805,994 B1Related patent
US 9,870,966 B1This patent

From the US filing history. Foreign family members aren’t listed.