Vertical fin field effect transistor (V-FinFET), semiconductor device having V-FinFET and method of fabricating V-FinFET

A semiconductor device, comprising:

• a first vertical field effect transistor (V-FinFET),
• wherein the first V-FinFET includes:
• a substrate having a lower source/drain (S/D);
• a first fin structure disposed on an upper surface of the lower S/D, wherein the first fin structure includes a sidewall having a lower sidewall portion, an upper sidewall portion and a center sidewall portion positioned therebetween;
• an upper S/D disposed on an upper surface of the first fin structure;
• a lower spacer disposed on the lower sidewall portion;
• a first upper spacer disposed on the upper sidewall portion, wherein the first upper spacer includes a first sidewall which is in contact with the upper sidewall portion and a second sidewall;
• a stacked structure including a gate oxide layer and a first gate electrode,
• wherein the stacked structure is interposed between the first upper spacer and the lower spacer,
• wherein a first sidewall of the stacked structure is in contact with the sidewall of the first fin structure, and
• wherein a second sidewall of the stacked structure is vertically aligned with the second sidewall of the first upper spacer;
• and
• a second V-FinFET,
• wherein the second V-FinFET includes:
• a second fin structure on the substrate,
• wherein a second gate electrode of the first V-FinFET is interposed between the first fin structure and the second fin structure so that the first V-FinFET and the second V-FinFET share the second gate electrode.