Simultaneous formation of source/drain openings with different profiles

A method comprising:

• forming a first gate stack over a first portion of a semiconductor substrate;
• forming a second gate stack over a second portion of the semiconductor substrate;
• implanting the second portion of the semiconductor substrate with an etch-tuning element, wherein the first portion of the semiconductor substrate is covered during the implanting;
• and
• simultaneously etching the first portion and the second portion of the semiconductor substrate to form a first opening and a second opening, respectively, in the semiconductor substrate, a surface of at least one of the first opening or the second opening proximate to the first gate stack or the second gate stack, respectively, being a curved surface with more than one crystallographic plane, wherein during the simultaneously etching, portions of the semiconductor substrate implanted with the etch-tuning element have a different lateral etching rate than portions of the semiconductor substrate un-implanted with the etch-tuning element.

A method comprising:

• forming a first dummy gate stack over a first portion of a semiconductor substrate;
• forming a second dummy gate stack over a second portion of the semiconductor substrate;
• forming a gate spacer layer over the first dummy gate stack and the second dummy gate stack;
• masking the first portion of the semiconductor substrate with a photoresist;
• while the first portion of the semiconductor substrate is masked with the photoresist, implanting the second portion of the semiconductor substrate with an etch-retarding element;
• simultaneously etching the first portion and the second portion of the semiconductor substrate to form a first opening and a second opening, respectively, in the semiconductor substrate, a surface of at least one of the first opening or the second opening proximate to the first gate dummy stack or the second dummy gate stack, respectively, being a curved surface with more than one crystallographic plane, wherein during the simultaneously etching, portions of the semiconductor substrate implanted with the etch-retarding element have a lower lateral etching rate than portions of the semiconductor substrate un-implanted with the etch-retarding element, and the portions of the semiconductor substrate implanted with the etch-retarding element and the portions of the semiconductor substrate un-implanted with the etch-retarding element have a same vertical etching rate;
• epitaxially growing a first semiconductor region in the first opening;
• and
• epitaxially growing a second semiconductor region in the second opening.