System on chip material co-integration
AssigneeInternational Business Machines Corporation
InventorsTakashi Ando, Lukas Czornomaz, Pouya Hashemi, Alexander Reznicek
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Abstract
A method, and the resulting structure, of a semiconductor device where a first and second gate structure is formed above a Semiconductor-on-Insulator (SOI) material. Following any detrimental processes used to form the first gate structure, the base semiconductor material is exposed and the semiconductor material beneath the second gate structure is removed. A new semiconductor material is grown from the exposed base semiconductor material, and through the second gate structure, creating a device having FET and FinFET devices containing 2 different semiconductor materials.
Claims15
A method for forming a semiconductor device comprising:
- forming a first gate structure on a first region of a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate comprises a first semiconductor-on-insulator layer located on an insulator layer, and the insulator layer is located on a base semiconductor layer, and wherein the first gate structure comprises a first gate structure located above the first semiconductor-on-insulator layer, and a first source/drain sandwiching the first gate structure;
- forming a second gate structure in a second region of the semiconductor-on-insulator substrate, wherein the second gate structure is located above the first semiconductor-on-insulator layer;
- removing a first portion of the second region to expose a first growth portion of the base semiconductor layer in the second region;
- removing the first semiconductor-on-insulator layer in the second region, wherein removing the semiconductor-on-insulator layer comprises removing the semiconductor-on-insulator layer beneath the second gate structure forming a gate void;
- forming a second semiconductor-on-insulator layer through the gate void, wherein the second semiconductor-on-insulator layer is epitaxially grown from the first growth portion of the base semiconductor layer in the second region.
Dependencies are inferred from the claim text.