Formation of VFET and finFET

A method of forming a semiconductor structure, the method comprising:

• forming a plurality of fins on a substrate, wherein a first fin is located above a bottom source/drain in a VFET region, wherein a second fin is located in a finFET region, and wherein a first hard cap is located on the first fin and a second hard cap is located on the second fin;
• removing the second hard cap;
• depositing a gate metal and a gate dielectric surrounding the first fin and the first hard cap in the VFET region and surrounding the second fin in the finFET region;
• removing the gate metal and the gate dielectric above the first hard cap in the VFET region, thereby exposing a vertical surface of the first hard cap;
• forming a protective spacer adjacent to the vertical surface of the first hard cap, wherein a thickness of the protective spacer is greater than a thickness of the gate dielectric;
• forming a first gate in the VFET region and a second gate on the second fin in the finFET region from the gate metal and the gate dielectric;
• depositing a spacer layer over the finFET region and the VFET region, wherein depositing the spacer layer in the VFET region creates a first surface of the spacer layer from a portion of the spacer layer located above the first hard cap and a second surface of the spacer layer above the gate metal;
• forming an insulating layer above the spacer layer in the finFET region and the VFET region;
• removing the insulating layer located above the first surface of the spacer layer in the VFET region;
• forming a finFET source drain on the second fin in the finFET region;
• removing the protective spacer and the first hard cap;
• and
• forming a top source/drain on the first fin.

A method of forming a semiconductor structure, the method comprising:

• forming a plurality of fins on a substrate, wherein a first fin is located above a bottom source/drain in a VFET region, wherein a second fin is located in a finFET region;
• depositing a gate metal and a gate dielectric surrounding the first fin in the VFET region, and surrounding the second fin in the finFET region;
• removing the gate metal and the gate dielectric above the first fin in the VFET region, and exposing a vertical surface of the first fin;
• forming a protective spacer adjacent to the vertical surface of the first fin, wherein a thickness of the protective spacer is greater than a thickness of the gate dielectric;
• forming a first gate in the VFET region and a second gate the second fin in the finFET region from the gate metal and the gate dielectric;
• depositing a spacer layer over the finFET region and the VFET region, wherein depositing the spacer layer in the VFET region creates a first surface of the spacer layer in the portion of the spacer layer located above the first fin and a second surface of the spacer layer above the gate metal;
• forming an insulating layer above the spacer layer in the finFET region and the VFET region;
• removing the insulating layer located above the first surface of the spacer layer in the VFET region;
• forming a finFET source drain on the second fin in the finFET region;
• removing the protective spacer;
• and
• forming a top source/drain on the first fin.