Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device, the method comprising:

• providing a substrate comprising a first region and a second region;
• forming dummy gate structures on the substrate, wherein each of the dummy gate structures comprises a dummy gate and a gate mask disposed on an upper surface of the dummy gate, wherein spacers are disposed on opposite side surfaces of each of the dummy gate structures, and wherein each of the dummy gates has a first width in the first region and a second width in the second region, wherein the first width is different from the second width;
• forming an insulating interlayer on the gate mask and the spacer;
• performing a first polishing including chemical mechanical polishing on portions of the gate mask, the spacers, and the insulating interlayer, wherein a polishing ratio of the gate mask and the spacers to the insulating interlayer is 1:1 to 2:1;
• and
• performing a second polishing including chemical mechanical polishing on remaining portions of the gate mask and the insulating interlayer to stop polishing on the upper surfaces of the dummy gates, wherein a polishing ratio of the insulating interlayer to the dummy gate is 50:1 to 300:1.

A method of manufacturing a semiconductor device, the method comprising:

• forming dummy gate structures on a substrate, wherein each of the dummy gate structures comprises a dummy gate and a gate mask disposed on an upper surface of the dummy gate, and wherein spacers are disposed on at least two sides of each of the dummy gate structures;
• forming an insulating interlayer on each of the gate masks and each of the spacers;
• performing a first polishing including chemical mechanical polishing on portions of the gate mask and the insulating interlayer to form upper surfaces of remaining portions of the gate mask and the insulating interlayer to have a substantially same level, wherein a polishing ratio of the gate mask to the insulating interlayer is 1:1 to 2:1;
• and
• performing a second polishing including chemical mechanical polishing on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of dummy gates, wherein a polishing ratio of the insulating interlayer to the dummy gate is 50:1 to 300:1.