RC-stacked MOSFET circuit for high voltage (HV) electrostatic discharge (ESD) protection

A device, comprising:

• N ones of a field effect transistor (FET) stacked in series to provide an N-level stack, wherein N is an integer greater than 1,
• a first pad coupled to a first FET and a second pad coupled to an Nth FET;
• and
• a RC control circuit configured to cause a short circuit between the first pad and the second pad in response to an electrostatic discharge (ESD) event, wherein the RC control circuit is configured to concurrently provide sufficient voltage to control the N ones of the FET, wherein the N ones of the FET are turned on by parasitic conduction to cause the short circuit, wherein the RC control circuit includes
• at most N capacitors coupled in series between the second pad and a gate of the first FET, wherein a value of the at most N capacitors is configured to provide a uniform gate potential to the N ones of the FET, and
• N resistors corresponding to the N ones of the FET respectively, wherein a first resistor is coupled between the gate of the first FET and the first pad, wherein the N resistors are configured to provide the sufficient voltage to a gate of each one of the N ones of the FET respectively in response to the ESD event, thereby triggering the parasitic conduction to close the N ones of the FET in a cascaded manner.

A method comprising:

• stacking N ones of a field effect transistor (FET) in series to provide an N-level stack, wherein N is an integer greater than 1;
• coupling a first pad to a first FET of the N ones of the FET;
• coupling a second pad to an Nth FET of the N ones of the FET;
• configuring a RC control circuit to provide a short circuit between the first pad and the second pad in response to an ESD event, the short circuit being configured to discharge energy from the ESD event to the first pad, wherein the RC control circuit is configured to include N capacitors coupled in series between the second pad and a gate of the first FET, wherein the RC control circuit is further configured to remove a configurable number of capacitors from the N capacitors to reduce surface area;
• and
• triggering parasitic conductance in the N ones of the FET, the parasitic conductance causing the N ones of the FET to close, thereby causing the short circuit.

A method comprising:

• providing a substrate;
• forming shallow trench isolation regions in the substrate;
• forming N-level RC stacked FET circuit with ESD protection which comprises
• forming N ones of field effect transistor (FET) and resistors in series on the substrate, wherein forming N ones of FET comprises providing a gate layer over the substrate, wherein the gate layer is patterned to define gates of the FETs and resistors, wherein the resistor is formed over the shallow trench isolation region which isolates adjacent FETs, and
• forming capacitor structures over the substrate;
• forming interlevel dielectric (ILD) and intermetal dielectric (IMD) layers over the substrate;
• and
• forming interconnects which include metal lines and via contacts in the ILD and IMD layers, wherein the interconnects couple the gates, capacitors and resistors to form the N-level RC stacked FET circuit.