Semiconductor device and manufacturing method thereof

A method of manufacturing a p-type metal-oxide-semiconductor (PMOS) fin field effect transistor (FinFET), the method comprising:

• forming a fin structure over a substrate, the fin structure extending in a first direction in plan view;
• forming an isolation insulating layer over the substrate so that a lower portion of the fin structure is embedded in the isolation insulating layer and an upper portion of the fin structure is exposed from the isolation insulating layer;
• forming a gate structure over a part of the fin structure, the gate structure extending in a second direction crossing the first direction in plan view;
• recessing an upper portion of the fin structure not covered by the gate structure;
• forming a first epitaxial layer on the recessed fin structure, the first epitaxial layer comprising Si1-xGex;
• forming a second epitaxial layer on the first epitaxial layer, the second epitaxial layer comprising Si1-yGey;
• forming a third epitaxial layer on the second epitaxial layer, the third epitaxial layer comprising Si1-zGez;
• forming a metal layer on the third epitaxial layer, the metal layer comprising at least one of Ti, Co and Ni;
• and
• forming an alloy layer of Si, Ge and the at least one of Ti, Co and Ni by a reaction of the third epitaxial layer and the metal layer,
• wherein x is smaller than y, and z is smaller than y.

A semiconductor device comprising:

• an isolation insulating layer disposed over a substrate;
• a fin structure disposed over the substrate, the fin structure extending in a first direction in plan view;
• a gate structure disposed over a part of the fin structure, the gate structure extending in a second direction crossing the first direction;
• a source/drain structure;
• and
• a source/drain contact, wherein:
• the source/drain structure includes:
• a first epitaxial layer comprising Si1-xGex;
• a second epitaxial layer disposed on the first epitaxial layer and comprising Si1-yGey;
• and
• a third epitaxial layer disposed on the second epitaxial layer and comprising Si1-zGez,
• z is smaller than y, and x is smaller than y, and
• an alloy layer comprising Si, Ge and Ti is formed between the third epitaxial layer and the source/drain contact.