Semiconductor memory device for performing a post package repair operation and operating method thereof

A semiconductor memory device comprising:

• a fuse array circuit including a row fuse region which includes a plurality of row fuse sets, each for programming a row address of a fail cell, and a column fuse region which includes a plurality of column fuse sets, each for programming a column address of the fall cell;
• an address latch block suitable for storing a fail address including a row address, a column address, a bank address and mat information in response to a repair mode signal;
• a control signal generation block suitable for generating a boot-up signal and a rupture signal in response to an active signal and a write signal, in response to the repair mode signal;
• a fail region search unit suitable for searching the row fuse region and the column fuse region corresponding to the fail address and generating a row region signal and a plurality of column region signals, in response to a counting signal which is generated by counting a clock signal, when the boot-up signal is enabled;
• a fuse set latch unit suitable for storing unused row fuse information and unused column fuse information based on the row region signal, the plurality of column region signals and fuse information outputted from the fuse array circuit, and selectively outputting the stored unused row or column fuse information in response to an up and down mat signal and a row and column select signal;
• and
• a rupture control block suitable for controlling the fail address to be programmed in a row fuse set or a column fuse set corresponding to the unused row or column fuse information, in response to the rupture signal.