# US 9,870,834 B2 · Error characterization and mitigation for 16nm MLC NAND flash memory under total ionizing dose effect > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,870,834 B2 - Document ID: US9870834B2 - Status: Granted - Kind: B2 - Application number: 15/298,171 - Filed: 2016-10-19 - Published: 2017-04-20 - Granted: 2018-01-16 - Earliest claimed: 2015-10-19 - Assignees: California Institute of Technology - Applicants: California Institute of Technology - Inventors: Yue Li; Jehoshua Bruck - Web page: https://patentgrep.com/patent/US9870834B2 ## CPC - G11C 16/3495: {Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically} - G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/10: Programming or data input circuits - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 29/44: Indication or identification of errors, e.g. for repair - G11C 2029/0409: {Online test} - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count. ## Claims ### Claim 1 A data device comprising: a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme; and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the data device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count. ### Claim 2 (depends on 1) The data device as in claim 1, wherein the selected operating mode for data scrubbing comprises one of an MLC (multi-level cell) scrubbing scheme, an E-SLC (enhanced single-level cell) scrubbing scheme, or an SLC-IPR (single level cell in-place rewriting) scrubbing scheme. ### Claim 3 (depends on 2) The data device as in claim 2, wherein the MLC scrubbing utilizes sequential MLC programming to set a charge level of each cell of the memory according to four or more charge levels. ### Claim 4 (depends on 2) The data device as in claim 2, wherein the E-SLC scrubbing utilizes only two states of available charge level states in each cell of the memory. ### Claim 5 (depends on 2) The data device as in claim 2, wherein the SLC-IPR scrubbing does not utilize block erasure for rewriting a cell and utilizes in-place rewriting of charge level states in each cell of the memory. ### Claim 6 (depends on 1) The data device as in claim 1, wherein the memory controller further performs data operations with the memory in accordance with the predetermined rank modulation scheme. ### Claim 7 (depends on 1) The data device as in claim 1, wherein the selected operating mode for data scrubbing utilizes only a high voltage state and a low voltage state for cells of the memory, comprising two voltage levels for each of the memory cells out of four voltage levels that are available for each of the memory cells. ### Claim 8 (depends on 1) The data device as in claim 1, wherein the selected operating mode for data scrubbing is configured to perform a data storage operation without first performing a block erasure operation. ### Claim 9 A computer method of operating a data device, the method comprising: receiving a current error count at a memory controller from an error decoder of the data device for one or more data operations of the data device, the error count indicating errors detected in a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme; and selecting an operating mode for data scrubbing in accordance with the received error count and a program cycles count. ### Claim 10 (depends on 9) The method as in claim 9, wherein the selected operating mode for data scrubbing comprises one of an MLC (multi-level cell) scrubbing scheme, an E-SLC (enhanced single-level cell) scrubbing scheme, or an SLC-IPR (single level cell in-place rewriting) scrubbing scheme. ### Claim 11 (depends on 10) The data device as in claim 10, wherein the MLC scrubbing utilizes sequential MLC programming to set a charge level of each cell of the memory according to four or more charge levels. ### Claim 12 (depends on 10) The data device as in claim 10, wherein the E-SLC scrubbing utilizes only two states of available charge level states in each cell of the memory. ### Claim 13 (depends on 10) The data device as in claim 10, wherein the SLC-IPR scrubbing does not utilize block erasure for rewriting a cell and utilizes in-place rewriting of charge level states in each cell of the memory. ### Claim 14 (depends on 9) The method as in claim 9, wherein the memory controller further performs data operations with the memory in accordance with the predetermined rank modulation scheme. ### Claim 15 (depends on 9) The method as in claim 9, wherein the selected operating mode for data scrubbing utilizes only a high voltage state and a low voltage state for cells of the memory, comprising two voltage levels for each of the memory cells out of four voltage levels that are available for each of the memory cells. ### Claim 16 (depends on 9) The method as in claim 9, wherein the selected operating mode for data scrubbing is configured to perform a data storage operation without first performing a block erasure operation.