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US 9,870,831 B2Granted
Semiconductor integrated circuit adapted to output pass/fail results of internal operations
AssigneeToshiba Memory Corporation
InventorsHiroshi Nakamura, Kenichi Imamiya, Toshio Yamamura, Koji Hosono, Koichi Kawai
Life of this patent
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Abstract
In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
Claims19
A nonvolatile semiconductor memory device comprising;
- a plurality of memory cells or a plurality of memory cell units each including a plurality of memory cells;
- a memory cell array including the plurality of memory cells or the plurality of memory cell units being arranged to form an array;
- a bit line;
- a bit line control circuit;
- and
- a data output control circuit;
- wherein a first operation is performed in response to an input of a first command or an input of a first command sequence, and after the input of the first command or the input of the first command sequence, a first ready/busy signal goes from a ready state to a busy state in a first timing, and then the first ready/busy signal goes from a busy state to a ready state in a second timing before the first operation is completed, the first operation includes a first read operation in which data stored in at least a portion of the plurality of memory cells or the plurality of memory cell units are read and stored in the bit line control circuit or the data output control circuit;
- wherein a second operation is performed in response to an input of a second command, address input and an input of a third command, and after the input of the second command, the address input and the input of the third command, the first ready /busy signal goes from a ready state to a busy state in a third timing, and then the first ready/busy signal is kept to a busy state until the second operation is completed, the second operation includes a second read operation in which data stored in at least a portion of the plurality of memory cells or the plurality of memory cell units are read and stored in the bit line control circuit or the data output control circuit;
- and
- wherein the first command, the second command and the third command are different from one another, the input of the first command sequence is different from the input of the second command, address input and the input of the third command, and the first command sequence includes the first command.
7 more elements
Dependencies are inferred from the claim text.