Non-volatile semiconductor memory and erasing method thereof
AssigneeWinbond Electronics Corp.
InventorsKatsutoshi Suito, Riichiro Shirota
Life of this patent
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Abstract
An erasing method of a nonvolatile semiconductor memory device of the disclosure includes erasing data of a selected memory cell (step S100); immediately applying a programming voltage lower than a programming voltage in a programming time to all control gates of the selected memory cell after the erasing step, thereby performing a week programming (step S110); performing a erasing verification of the selected memory cell (step S120).
Claims15
An erasing method of a non-volatile semiconductor memory device, the non-volatile semiconductor memory device comprising a memory array that forms a plurality of memory cells, wherein the memory cell comprises a control gate, a charge storage layer and a channel region, the erasing method of the non-volatile semiconductor memory device comprising:
- selecting step:
- selecting the memory cell to be erased from the memory array;
- erasing step:
- applying an erasing voltage to the channel region of the selected memory cell, and erasing data of the charge storage layer of the selected memory cell;
- and
- weak programming step:
- immediately applying a weak programming voltage lower than a programming voltage in a programming time to all of the control gates of the selected memory cell after the erasing step, thereby uniformly performing week programming to the selected memory cell,
- an erasing verification step:
- performing erasing verification of the selected memory cell after the weak programming step, and a present weak programming voltage is smaller than a previous weak programming voltage.
A non-volatile semiconductor memory device, comprising:
- a memory array, forming a plurality of memory cells, wherein the memory cell comprises a control gate, a charge storage layer and a channel region;
- a selection component, selecting the memory cell to be erased from the memory array;
- and
- an erasing component, erasing data of the memory cell selected by the selection component,
- wherein the erasing component applies an erasing voltage to the channel region of the selected memory cell to erase data of the charge storage layer of the selected memory cell, and after the erasing voltage is applied, the erasing component immediately applies a weak programming voltage lower than a programming voltage in a programming time to all of the control gates of the selected memory cell, so as to uniformly perform week programming to the selected memory cell,
- wherein the erasing component executes erasing verification of the selected memory cell after the weak programming, and the erasing component makes a present weak programming voltage to be smaller than a previous weak programming voltage.
A non-volatile semiconductor memory device, comprising:
- a memory array, forming a plurality of memory cells, wherein the memory cell comprises a control gate, a charge storage layer and a channel region;
- a selection component, selecting the memory cell to be erased from the memory array;
- and
- an erasing component, erasing data of the memory cell selected by the selection component,
- wherein the erasing component applies an erasing voltage to the channel region of the selected memory cell to erase data of the charge storage layer of the selected memory cell, and after the erasing voltage is applied, the erasing component immediately applies a weak programming voltage lower than a programming voltage in a programming time to all of the control gates of the selected memory cell, so as to uniformly perform week programming to the selected memory cell,
- wherein the erasing component executes erasing verification of the selected memory cell after the weak programming, and the erasing component makes an applying time of a present weak programming voltage to be shorter than an applying time of a previous weak programming voltage.
Dependencies are inferred from the claim text.