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US 9,870,827 B2Granted
Semiconductor device and electronic device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsTakashi Nakagawa, Hiroki Inoue, Fumika Akasawa, Yoshiyuki Kurokawa
Life of this patent
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Abstract
A semiconductor device with an arithmetic processing function is provided. The semiconductor device includes a first circuit and a second circuit each having a function of performing one-dimensional discrete cosine transform. By directly inputting output data of the first circuit to the second circuit, two-dimensional discrete cosine transform can be performed immediately. A memory cell array included in the first circuit is divided into a plurality of memory blocks. In the case where a selection transistor is provided in the memory block, data processing can be performed in each memory block.
Claims29
A semiconductor device comprising:
- a first circuit including first memory blocks, a first reference memory block, a third circuit, a fourth circuit, a fifth circuit, a sixth circuit, and a seventh circuit;
- and
- a second circuit including operation blocks, a second reference memory block, an eighth circuit, a ninth circuit, and a tenth circuit,
- wherein the first memory blocks are arranged in a matrix,
- wherein the first memory blocks and the first reference memory block each include a first memory cell,
- wherein the first memory blocks are configured to store first data,
- wherein the third circuit is configured to select the first memory cell to which the first data is written,
- wherein the fourth circuit is configured to supply the first data,
- wherein the fifth circuit is configured to supply a potential corresponding to a coefficient used for operation to the first memory blocks and the first reference memory block,
- wherein the sixth circuit is configured to bring the first reference memory block and the seventh circuit into conduction and to bring a selected first memory block and the seventh circuit into conduction,
- wherein the seventh circuit is configured to output second data obtained by operation using a signal output from the first reference memory block and a signal output from the selected first memory block to the second circuit,
- wherein the operation blocks are provided in a row direction,
- wherein each of the operation blocks includes a second memory block and a third memory block,
- wherein the second memory block, the third memory block, and the second reference memory block each include a second memory cell,
- wherein the second memory block and the third memory block are each configured to store the second data,
- wherein the eighth circuit is configured to select the second memory cell to which the second data is written,
- wherein the ninth circuit is configured to supply a potential corresponding to a coefficient used for operation to the second memory block or the third memory block and the second reference memory block,
- wherein the tenth circuit is configured to output third data obtained by operation using a signal output from the second reference memory block and a signal output from a selected second memory block or the third memory block,
- wherein the second data is alternately input to the second memory block and the third memory block, and
- wherein one of the second memory block and the third memory block is configured to perform operation while the second data is input to the other of the second memory block and the third memory block.
17 more elements
A semiconductor device comprising:
- a first circuit including first memory blocks, a first reference memory block, a third circuit, a fourth circuit, a fifth circuit, a sixth circuit, and a seventh circuit;
- and
- a second circuit including operation blocks, a second reference memory block, an eighth circuit, a ninth circuit, and a tenth circuit,
- wherein the first memory blocks are arranged in a matrix and includes a first transistor,
- wherein the first reference memory block includes a second transistor,
- wherein the first memory blocks and the first reference memory block each include a first memory cell including a third transistor, a fourth transistor, and a first capacitor,
- wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and one electrode of the first capacitor,
- wherein the other of the source and the drain of the third transistor is electrically connected to the fourth circuit,
- wherein a gate of the third transistor is electrically connected to the third circuit,
- wherein the other electrode of the first capacitor is electrically connected to the fifth circuit,
- wherein one of a source and a drain of the fourth transistor is electrically connected to a power supply line,
- wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the first transistor provided in the same column,
- wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the second transistor,
- wherein a gate of the first transistor and a gate of the second transistor are electrically connected to the sixth circuit,
- wherein the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor are electrically connected to the seventh circuit,
- wherein the operation blocks are provided in a row direction,
- wherein each of the operation blocks includes a second memory block and a third memory block, and
- wherein the second memory block, the third memory block, and the second reference memory block each include a second memory cell.
15 more elements
A semiconductor device comprising:
- a memory block including a first memory cell, a second memory cell, and a first transistor,
- wherein the first memory cell including:
- a second transistor;
- a third transistor;
- and
- a first capacitor;
- wherein one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor and an electrode of the first capacitor,
- wherein the second memory cell including:
- a fourth transistor;
- a fifth transistor;
- and
- a second capacitor;
- wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the fifth transistor and an electrode of the second capacitor,
- wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fifth transistor.
11 more elements
A semiconductor device comprising:
- a memory block including a first memory cell, a second memory cell, and a first transistor,
- wherein the first memory cell including:
- a second transistor;
- a third transistor;
- a first photoelectric conversion element;
- and
- a first capacitor;
- wherein one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor, an electrode of the first capacitor, and an electrode of the first photoelectric conversion element,
- wherein the second memory cell including:
- a fourth transistor;
- a fifth transistor;
- a second photoelectric conversion element;
- and
- a second capacitor;
- wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the fifth transistor, an electrode of the second capacitor, and an electrode of the second photoelectric conversion element,
- wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fifth transistor.
13 more elements
Dependencies are inferred from the claim text.