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US 9,870,821 B2Granted
Electronic device
AssigneeSK hynix Inc.
InventorHyuck-Sang Yim
Life of this patent
Estimating the term…
Abstract
An electronic device including a semiconductor memory is disclosed. The semiconductor memory includes a read path including a unit storage cell; a reference path including a unit reference cell; read circuit suitable for comparing a read current flowing on the read path with a reference current flowing on the reference path in response to a read voltage and a reference voltage, and sensing data stored in the unit storage cell based on the comparison result; a first replica path suitable for modeling the read path; and a reference voltage generation unit suitable for generating the reference voltage corresponding to a first replica current flowing on the first replica path in response to the read voltage.
Claims18
An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises:
- a read path including a unit storage cell;
- a reference path including a unit reference cell;
- a read circuit suitable for comparing a read current flowing on the read path with a reference current flowing on the reference path to produce a comparison in response to a read voltage and a reference voltage, and for sensing data stored in the unit storage cell based on the comparison;
- a first replica path suitable for modeling the read path;
- and
- a reference voltage generation unit suitable for generating the reference voltage corresponding to a first replica current flowing on the first replica path in response to the read voltage,
- wherein the semiconductor memory further comprises a second replica path modeling the reference path, and
- wherein the reference voltage generation unit generates a second replica current flowing on the second replica path by mirroring the first replica current, and generates the reference voltage corresponding to the generated second replica current.
5 more elements
An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises:
- a read path coupled to a low voltage terminal, and including a unit storage cell;
- a reference path coupled to the low voltage terminal, and including a unit reference cell;
- a sensing unit coupled to a high voltage terminal, wherein the sensing unit is configured to compare a read current flowing on the read path with a reference current flowing on the reference path to produce a comparison, and sense data stored in the unit storage cell based on the comparison;
- a read current clamping unit coupled between the sensing unit and the read path, wherein the read current clamping unit is configured to clamp the read current in response to a read voltage;
- a reference current clamping unit coupled between the sensing unit and the reference path, the reference current clamping unit configured to clamp the reference current in response to a reference voltage;
- a first replica path coupled to the low voltage terminal, the first replica path configured to model the read path;
- a second replica path coupled to the low voltage terminal, the second replica path configured to model the reference path;
- a current mirroring unit coupled to the high voltage terminal, the current mirroring unit configured to generate a second replica current flowing on the second replica path by mirroring a first replica current flowing on the first replica path;
- a first replica current clamping unit coupled between the current mirroring unit and the first replica path, the first replica current clamping unit configured to clamp the first replica current in response to the read voltage;
- and
- a second replica current clamping unit between the current mirroring unit and the second replica path, the second replica current clamping unit configured to clamp the second replica current in response to the reference voltage.
8 more elements
An electronic device comprising a semiconductor memory device which includes:
- a read voltage generation block configured to generate a read voltage;
- a reference voltage generation block configured to generate, in response to the read voltage, a reference voltage corresponding to a first replica current flowing on a first replica path including a high level replica path and a low level replica path;
- and
- a memory block including one or more read blocks in electrical communication with the read voltage generation block and the reference voltage generation block, each read block including:
- a unit storage cell,
- a unit reference cell, and
- read circuitry in electrical communication with the unit storage cell and the unit reference cell, the read circuitry configured to sense data stored in the unit storage cell in response to the read voltage applied to the unit storage cell and the reference voltage applied to the unit reference cell;
- wherein the reference voltage generation block includes a first replica path suitable for modeling a read path including the unit storage cell and a second replica path modeling the reference path including the unit reference cell of a corresponding read block,
- wherein the reference voltage generation block generates a second replica current flowing on the second replica path by mirroring the first replica current, and generates the reference voltage corresponding to the generated second replica current, and
- wherein the reference voltage generation block generates the first replica current by averaging a first current flowing on the high level replica path including the unit storage cell in which data of a logic high level is stored and a second current flowing on the low level replica path including the unit storage cell in which data of a logic low level is stored.
7 more elements
Dependencies are inferred from the claim text.