Apparatuses and methods for current limitation in threshold switching memories

An apparatus, comprising:

• a memory cell coupled to a first pair of decoder circuits via a first access line and a second access line;
• and
• a control circuit coupled to the first pair of decoder circuits, and wherein the control circuit is configured to sequentially activate the first pair of decoder circuits, wherein a first one of the first pair of decoder circuits associated with a first parasitic load is activated before a second one of the first pair of decoder circuits associated with a second parasitic load, wherein the first parasitic load is based on a first distance to the memory cell that is greater than a second distance to the memory cell associated with the second parasitic load.

A method, comprising:

• non-simultaneously activating a first one of a pair of decoder circuits coupled to a memory cell via a respective access line based on a first parasitic load associated with a first distance to the memory cell from the first one of the pair of decoder circuits;
• and
• non-simultaneously activating a second one of a pair of decoder circuits coupled to the memory cell via the respective access line based on a second parasitic load associated with a second distance to the memory cell from the second one of the pair of decoder circuits.