Semiconductor device and information reading method
AssigneeSony Semiconductor Solutions Corporation
InventorTsunenori Shiimoto
Life of this patent
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Abstract
A semiconductor device including a memory device configured to take a plurality of resistance states that are distinguishable from one another; a bias application section configured to apply, in a bias application period, a bias signal to the memory device; and a determination section configured to determine a resistance state of the memory device on the basis of a detection signal, in which the detection signal is generated in the memory device to which the bias signal is applied. The bias application section sets a length of the bias application period in accordance with a resistance value of the memory device, when the resistance state determined by the determination section is predetermined one of the resistance states.
Claims18
A memory device, comprising:
- a plurality of memory cells, each of the memory cells configured to output a voltage signal as a detection signal and including a first electrode, a memory layer, and a second electrode;
- a reference memory cell, the reference memory cell configured to output a reference voltage;
- a bias application section configured to provide a bias signal which is applied to one of the electrodes of the memory cells and, for each memory cell, generate the detection signal;
- a determination section in electrical communication with the memory cells and configured to compare each detection signal with the reference voltage and output a respective result;
- and
- a signal generation section configured to generate a read control signal that is used to control operation of the determination section,
- wherein,
- the bias application section includes a pulse signal generation circuit configured to generate a pulse signal and an application circuit configured to selectively apply the bias signal to the memory cells based on the pulse signal.
Dependencies are inferred from the claim text.