US 9,870,818 B1Granted

Separate read and write address decoding in a memory system to support simultaneous memory read and write operations

AssigneeQUALCOMM Incorporated

InventorManish Garg

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Abstract

Memory systems that provide separate read and write address decoding to support simultaneous memory read and write operations are disclosed. Separating read and write address decoding can avoid circuit conflicts for a simultaneous memory read and write operation even if employing single port memory bit cells. The read and write addresses of respective read and write operations are separately decoded into read and write row and column selects driven to a memory array so that simultaneous read and write operations are not affected by each other. To avoid a circuit conflict for a simultaneous read and write operation, the memory system is configured to prioritize a write row select over a read row select to drive a row of memory bit cells in the memory array. In this manner, that write operation will always be successful regardless of whether the read and write row select are to the same row.

Claims32

Dependent claims

A memory bit cell selection circuit for a memory system, the memory bit cell selection circuit configured to:

in response to a memory write operation:
receive a write row select indicating a memory bit cell row among a plurality of memory bit cell rows in a memory array corresponding to a memory write address for the memory write operation;
receive a write column select indicating a memory bit cell column among a plurality of memory bit cell columns in the memory array corresponding to the memory write address for the memory write operation;
select the memory bit cell column of memory bit cells in the memory array addressed by the write column select;
and
generate a read/write row select indicating the memory write operation;
and
select the memory bit cell row of memory bit cells in the memory array addressed by the write row select in response to the read/write row select indicating the memory write operation;
and
in response to a memory read operation:
receive a read row select indicating a memory bit cell row among the plurality of memory bit cell rows in the memory array corresponding to a memory read address for the memory read operation;
receive a read column select indicating a memory bit cell column among the plurality of memory bit cell columns in the memory array corresponding to the memory read address for the memory read operation;
select the memory bit cell column of memory bit cells in the memory array addressed by the read column select;
generate a read/write row select indicating the memory read operation in response to the memory write operation not being present for the memory read operation;
and
select the memory bit cell row of the memory bit cells in the memory array addressed by the read row select in response to the read/write row select indicating the memory read operation.

13 more elements

A method of performing a memory read and write operation to a memory array in a memory system, comprising:

receiving a write row select indicating a memory bit cell row among a plurality of memory bit cell rows in a memory array corresponding to a memory write address for a memory write operation;
receiving a write column select indicating a memory bit cell column among a plurality of memory bit cell columns in the memory array corresponding to the memory write address for the memory write operation;
receiving a read row select indicating a memory bit cell row among the plurality of memory bit cell rows in the memory array corresponding to a memory read address for a memory read operation;
receiving a read column select indicating a memory bit cell column among the plurality of memory bit cell columns in the memory array corresponding to the memory read address for the memory read operation;
selecting the memory bit cell column of memory bit cells in the memory array addressed by the write column select;
selecting the memory bit cell column of memory bit cells in the memory array addressed by the read column select;
generating a read/write row select indicating the memory write operation in response to the memory write operation being present;
and
selecting the memory bit cell row of the memory bit cells in the memory array addressed by the write row select in response to the read/write row select indicating the memory write operation.

6 more elements

A memory system, comprising:

a memory array comprising a plurality of memory bit cells organized into a plurality of memory bit cell rows and a plurality of memory bit cell columns;
a read/write decoder circuit configured to:
decode a memory read address in a memory read operation into:
a read row select indicating a memory bit cell row among the plurality of memory bit cell rows in the memory array corresponding to the memory read address;
and
a read column select indicating a memory bit cell column among the plurality of memory bit cell columns in the memory array corresponding to the memory read address;
and
decode a memory write address in a memory write operation into:
a write row select indicating a memory bit cell row among the plurality of memory bit cell rows in the memory array corresponding to the memory write address;
and
a write column select indicating a memory bit cell column among the plurality of memory bit cell columns in the memory array corresponding to the memory write address;
and
at least one memory bit cell selection circuit each configured to:
in response to the memory write operation:
select a memory bit cell column among the plurality of memory bit cell columns in the memory array addressed by the write column select;
generate a read/write row select indicating the memory write operation;
and
select a memory bit cell row among the plurality of memory bit cell rows in the memory array addressed by the write row select in response to the read/write row select indicating the memory write operation;
and
in response to the memory read operation:
select a memory bit cell column among the plurality of memory bit cell columns in the memory array addressed by the read column select;
generate a read/write row select indicating the memory read operation in response to the memory write operation not being present for the memory read operation;
and
select a memory bit cell row of memory bit cells in the memory array addressed by the read row select in response to the read/write row select indicating the memory read operation.

21 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/429,842Filed 10 Feb 2017 · us provisional application
Priority: 4 Oct 2016
Granted: 16 Jan 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 11/419
For memory cells of the field-effect type: read-write [R-W] circuits
G11C 7/1015
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: read-write modes for single port memories, i.e.…
G11C 8/08
Arrangements for selecting an address in a digital store: word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down…
G11C 8/10
Arrangements for selecting an address in a digital store: decoders