US 9,870,816 B2Granted

Method for driving semiconductor device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsTatsuya Onuki, Kiyoshi Kato

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Abstract

A semiconductor device includes SRAM that stores data in an inverter loop including a CMOS inverter, transistors electrically connected to an input terminal or an output terminal of the CMOS inverter, and capacitors electrically connected to the corresponding transistors. The semiconductor device is configured to hold potentials corresponding to data at nodes between the transistors and the corresponding capacitors in a period during which supply of power to the CMOS inverter stops. In the period during which power supply stops, the potential of a wiring applying a low power supply potential is made equal to a high power supply potential to make the potentials of the input and output terminals of the CMOS inverter equal to the high power supply potential. The potentials corresponding to the data held at the nodes are applied to the input and output terminals of the CMOS inverter to restart power supply.

Claims7

Dependent claims

A method for driving a semiconductor device comprising an SRAM, a first transistor electrically connected to an input terminal of the SRAM, and a second transistor electrically connected to an output terminal of the SRAM comprising the steps of:

applying a first potential to a first power supply line;
applying a floating potential to a second power supply line;
applying a high-level potential to gates of the first transistor and the second transistor;
and
applying a second potential to the second power supply line when the high-level potential is applied to the gates of the first transistor and the second transistor,
wherein the first potential is higher than the second potential,
wherein the SRAM comprises a third transistor, a fourth transistor, a fifth transistor and a sixth transistor,
wherein the first power supply line is directly electrically connected to each of the third transistor and the fourth transistor, and
wherein the second power supply line is directly electrically connected to each of the fifth transistor and the sixth transistor.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/527,310Filed 29 Oct 2014
Priority: JP 2013-22734931 Oct 2013
Published: US 2015/0117093 A130 Apr 2015
Granted: 16 Jan 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 11/417
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction: for memory cells of the field-effect type
G11C 11/412
Forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt…
G11C 11/404
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with one charge-transfer gate, e.g. MOS transistor, per cell
G11C 11/405
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with three charge-transfer gates, e.g. MOS transistors,…