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US 9,870,815 B2Granted
Structure and method for a SRAM circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
The present disclosure provides an integrated circuit formed in a semiconductor substrate. The integrated circuit includes a first static random access memory (SRAM) cell having a first cell size; and a second SRAM cell having a second cell size greater than the first cell size. The first SRAM cell includes first n-type field effect transistors (nFETs) each having a first gate stack. The second SRAM cell includes second nFETs each having a second gate stack different from the first gate stack.
Claims20
A device comprising:
- a first static random access memory (SRAM) cell having a first cell size, the first SRAM cell includes a first group of field effect transistors each having a first gate stack;
- and
- a second SRAM cell having a second cell size greater than the first cell size, wherein the second SRAM cell includes a second group of field effect transistors each having a second gate stack different from the first gate stack, wherein the second gate stack is different from the first gate stack in at least one of gate electrode material and gate dielectric material.
A device comprising:
- a first static random access memory (SRAM) cell having:
- a first two pull-down devices that are part of a first two cross-coupled inverters for data storage, and
- a first two pass-gate devices configured with the first two cross-coupled inverters to form first ports for data access;
- and
- a second SRAM cell having:
- a second two pull-down devices that are part of a second two cross-coupled inverters for data storage;
- and
- a second two pass-gate devices configured with the second two cross-coupled inverters to form second ports for data access, and
- wherein the first SRAM cell includes a first number of field effect transistors and the second SRAM cell includes a second number of field effect transistors that is different than the first number of field effect transistors, and
- wherein one of the field effect transistors of the first SRAM cell has a first gate stack and one of the field effect transistors of the second SRAM cell has a second gate stack, wherein the second gate stack is different from the first gate stack in at least one of gate electrode material and gate dielectric material.
7 more elements
A device comprising:
- a first static random access memory (SRAM) cell having a first cell size, the first SRAM cell includes a first group of fin field effect transistors (FinFETs) each having a first gate stack;
- and
- a second SRAM cell having a second cell size greater than the first cell size, wherein the second SRAM cell includes a second group of FinFETs each having a second gate stack different from the first gate stack, wherein the second gate stack is different from the first gate stack in at least one of gate electrode material and gate dielectric material.
Dependencies are inferred from the claim text.