Memory system with timing overlap mode for activate and precharge operations
AssigneeEverspin Technologies, Inc.
InventorsThomas Andre, Syed M. Alam, Halbert S. Lin
Life of this patent
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Abstract
In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
Claims20
A system, comprising:
- a memory, including:
- an array of memory cells;
- a cache coupled to the array of memory cells, wherein in response to an activate command received by the memory, the memory is configured to open a page of memory by loading data in the page from the array to the cache, wherein in response to a precharge command received by the memory, the memory is configured to close a previously opened page of memory by writing the contents of the cache to the array;
- and
- a memory controller coupled to the memory, wherein the memory controller is configured to:
- issue a first activate command to the memory to open a first page;
- after issuing the first activate command to open the first page, issue a first precharge command to the memory to close the first page;
- and
- after issuing the first precharge command and prior to the memory completing operations to close the first page, issue a second activate command to the memory to open a second page, wherein the memory delays execution of operations associated with the second activate command while the operations to close the first page are still being performed.
A system, comprising:
- a magnetic memory, including:
- an array of magnetic memory cells;
- a cache coupled to the array of magnetic memory cells, wherein in response to an activate command received by the magnetic memory, the magnetic memory is configured to open a page of memory by loading data in the page from the array to the cache, wherein the magnetic memory requires a first number of clock cycles to open the page;
- wherein in response to a precharge command received by the magnetic memory, the magnetic memory is configured to close a previously opened page of memory by writing the contents of the cache to the array, wherein the magnetic memory requires a second number of clock cycles to close the previously opened page;
- and
- a memory controller coupled to the magnetic memory, the memory controller including:
- a first register that stores a value representative of a third number of clock cycles the memory controller makes available to the magnetic memory to complete operations associated with each precharge command, wherein a maximum value for the third number of clock cycles is less than the second number of clock cycles required by the magnetic memory to close the page;
- and
- a second register that stores a value representative of a fourth number of clock cycles the memory controller makes available to the magnetic memory to complete operations associated with each activate command;
- wherein the memory controller is configured to:
- issue a first activate command to the magnetic memory to open a first page;
- after issuing the first activate command to open the first page, issue a first precharge command to the magnetic memory to close the first page;
- and
- after the third number of clock cycles following issuance of the first precharge command and prior to the magnetic memory completing operations to close the first page in response to the first precharge command, issue a second activate command to the magnetic memory to open a second page, wherein the magnetic memory delays execution of operations associated with the second activate command while the operations to close the first page are still being performed.
A method of operation of a system that includes a memory controller coupled to a memory, comprising:
- storing, in a first register on the memory controller, a value representing a maximum number of clock cycles available for the memory to complete operations associated with a precharge command;
- storing, in a second register on the memory controller, a value representing a number of clock cycles available for the memory to complete operations associated with an activate command;
- issuing, by the memory controller, a first activate command to the memory;
- receiving, by the memory, the first activate command, wherein in response to the first activate command the memory opens a page corresponding to the first activate command by loading the first page from a memory array to a cache;
- after issuing the first activate command, issuing, by the memory controller a first precharge command;
- receiving by the memory, the first precharge command, wherein in response to the first precharge command, the memory closes the first page by writing the first page from the cache to the array, wherein the memory requires a number of clock cycles to close the first page that is greater than the maximum number of clock cycles represented by the value stored in the first register of the memory controller;
- after issuing the first precharge command, issuing, by the memory controller, a second activate command, wherein the second activate command is issued before the memory finishes closing the first page;
- and
- receiving, by the memory, the second activate command, wherein the memory delays execution of the second activate command until completion of closure of the first page.
Dependencies are inferred from the claim text.