Memory device for performing calibration operation
AssigneeSamsung Electronics Co., Ltd.
InventorsHyunui Lee, Won-joo Yun, Hye-seung Yu, In-dal Song
Life of this patent
Estimating the term…
Abstract
Provided is a memory device configured to perform a calibration operation without having a ZQ pin. The memory device includes a calibration circuit configured to generate a pull-up calibration code and a pull-down calibration code which termination of a data input/output pad for impedance matching in the data input/output pad is controlled. The calibration circuit performs a first calibration operation for trimming first and second reference resistors based on an external resistor to be connected to a pad, and a second calibration operation for generating the pull-up calibration code and the pull-down calibration code based on the trimmed second reference resistor.
Claims20
A calibration circuit of a memory device, the calibration circuit comprising:
- a first calibration circuit configured to generate a trimming code for trimming a first reference resistor, based on an external resistor to be connected to a pad of the memory device;
- and
- a second calibration circuit configured to trim a second reference resistor in response to the trimming code, and to generate a pull-up calibration code and a pull-down calibration code based on the trimmed second reference resistor,
- wherein the memory device includes a pull-up driver configured to receive the pull-up calibration code and a pull-down driver configured to receive the pull-down calibration code,
- wherein the pull-up driver and the pull-down driver are connected to a data input/output pad of the memory device, and
- wherein termination of the data input/output pad is controlled in response to the pull-up calibration code and the pull-down calibration code.
A memory device comprising:
- a memory buffer comprising conductive terminals to perform an external interfacing function of the memory device;
- and
- memory layers stacked on the memory buffer, electrically connected to the memory buffer via through substrate vias, and each of the memory layers comprising channels providing an interface independent from the memory buffer,
- wherein the memory buffer comprises a calibration circuit configured to trim a first reference resistor and a second reference resistor based on an external resistor to be connected to a conductive terminal, and to generate a pull-up calibration code and a pull-down calibration code based on the trimmed second reference resistor, and
- wherein termination of a data input/output pad (a DQ pad) of each of the channels is controlled in response to the pull-up calibration code and the pull-down calibration code.
A memory device comprising:
- a DQ pad;
- an output driver including a pull-up driver and a pull-down driver each connected to the DQ pad and configured to provide a data signal to the DQ pad;
- and
- a calibration circuit configured to generate a trimming code to trim a first reference resistor and a second reference resistor based on an external resistor to be connected to an internal pad, and configured to generate a pull-up calibration code and a pull-down calibration code provided to the pull-up driver and the pull-down driver, respectively, based on the trimmed second reference resistor,
- wherein the DQ pad is configured to be connected to outside of the memory device and the internal pad is configured to be not connected to outside of the memory device.
Dependencies are inferred from the claim text.