Display panel

A display panel, comprising:

• a pixel array, having a plurality of pixels;
• a gate driver circuit, coupled with the pixels to provide a plurality of gate signals, comprising:
• a plurality of shift registers, respectively receiving a first gate signal of the gate signals and a first clock signal of a plurality of clock signals, to respectively provide a first control signal and a second control signal, wherein the clock signals are sequentially enabled;
• and
• a plurality of demultiplexers, respectively receiving a plurality of second clock signals of the clock signals, and are coupled to the corresponding one of the shift registers to receive the first control signal and the second control signal provided by the corresponding one of the shift registers, wherein each of the demultiplexers are turned-on according to the first control signal provided by the corresponding one of the shift registers, to provide the gate signals according to the second clock signals, and each of the demultiplexers are cut-off according to the second control signal provided by the corresponding one of the shift registers,
• wherein each of the shift registers comprising:
• a first control circuit, receiving the first gate signal and the first clock signal, to enable the first control signal according to the first gate signal, and disable the first control signal according to the first clock signal, wherein an enabled period of the first gate signal does not overlap with an enabled period of the corresponding one of the second clock signal, wherein the first control circuit comprises:
• a first transistor, having a first end receiving a forward scan voltage, a second end providing the first control signal, and a control end receiving the first gate signal;
• and
• a second transistor, having a first end receiving a gate low voltage, a second end coupled to the second end of the first transistor, and a control end receiving the first clock signal;
• and
• a second control circuit, receiving the first gate signal and the first clock signal, to disable the second control signal according to the first gate signal, and enable the second control signal according to the first clock signal.