Gate circuit, driving method for gate circuit and display device using the same

A method for driving a gate driver including a plurality of stages, each receiving a clock signal and outputting a gate signal and a carry signal, one of the plurality of stages including a first transistor, of which a first terminal and a control terminal are connected to each other, and a carry signal of a stage before a previous stage is input to the first terminal and the control terminal and a second transistor, of which a gate signal of the previous stage is input to a first terminal, a control terminal is connected with a second terminal of the first transistor, and an output terminal is connected to a first node, comprising:

• applying a carry signal of the stage before the previous stage to the control terminal of the second transistor through the first transistor;
• inputting the gate signal of the previous stage to the first terminal of the second transistor;
• boosting the voltage difference between the control terminal and the output terminal of the second transistor during an enable time of the gate signal of the previous stage;
• and
• boosting a voltage of the first node during a rising time of the clock signal.

A display device including a display unit including a plurality of pixels connected to corresponding gate lines and a gate driver including a plurality of stages, each receiving a clock signal and outputting a gate signal to the gate line,

• wherein one of the plurality of stages comprises:
• a first transistor of which a first terminal and a control terminal are connected and a carry signal of a stage before a previous stage is input to the first terminal and the control terminal;
• and
• a second transistor, of which a gate signal of the previous stage is input to a first terminal, a control terminal is connected with a second terminal of the first transistor, and an output terminal is connected with a first node,
• the carry signal of the stage before the previous stage is applied to the control terminal of the second transistor through the first transistor, the gate signal of the previous stage is input to the first terminal of the second transistor,
• a voltage difference between the control terminal and the output terminal of the second transistor is boosted during an enable time of the gate signal of the previous stage, and
• a voltage of the first node is boosted during a rising time of the clock signal.