Method and apparatus for integrated circuit mask patterning
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
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Abstract
Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.
Claims20
A method comprising:
- receiving a design layout of an integrated circuit (IC), the design layout having a first main feature;
- and
- adding a negative assist feature to the design layout, wherein:
- the negative assist feature has a width,
- the negative assist feature divides the first main feature into a second main feature and a third main feature by the width, and
- the width is sub-resolution in a photolithography process;
- performing an optical proximity correction (OPC) process to the second main feature and the third main feature to optimize the design layout;
- and
- performing a mask rule checking (MRC) process to the optimized design layout.
A method, comprising:
- receiving a circuit design layout having a printing feature;
- identifying a negative optical proximity correction (OPC) feature corresponding to a portion of the printing feature to remove, wherein the negative OPC feature has a width that corresponds to a sub-resolution width;
- determining that the negative OPC feature complies with a mask rule check;
- based on determining that the negative OPC feature complies with the mask rule check, updating the circuit design layout to apply the negative OPC feature to the printing feature;
- and
- after updating the circuit design layout to apply the negative OPC feature, determining that the applying of the negative OPC feature to the printing feature produces a resulting feature that complies with the mask rule check.
A method comprising:
- receiving a circuit layout for a photolithographic mask, wherein the circuit layout includes a feature;
- identifying a portion of the feature to remove,
- determining that the portion complies with a mask rule check;
- removing the portion of the feature from the circuit layout based on determining that the portion complies with the mask rule check;
- performing the mask rule check on a result of removing the portion of the feature;
- performing a lithography process check on the result of removing the portion of the feature;
- and
- adjusting at least one of:
- a location or a size of the removed portion based on the lithography process check.
Dependencies are inferred from the claim text.