Snap-to valid pattern system and method

A method of providing a physical pattern at one of a plurality of layers in a semiconductor integrated circuit, the method comprising the steps of:

• creating a representation of the physical pattern at the one of the plurality of layers in the semiconductor integrated circuit, the physical pattern representation corresponding to a valid pattern defined by data;
• snapping an invalid pattern defined by other data into the valid pattern, the step of snapping including determining a valid size and a valid position that approximates an invalid size and an invalid position of the invalid pattern, wherein the valid pattern includes at least a valid size and a valid position, and wherein the valid pattern is obtained based upon a plurality of golden cell valid patterns, wherein the plurality of golden cell valid patterns contain every allowable pattern;
• and
• producing, based upon the other data and the determined valid size and valid position, the semiconductor integrated circuit that includes the physical pattern.