Method for automatically generating a netlist of an FPGA program
AssigneedSPACE digital signal processing and control engineering GmbH
InventorsHeiko Kalte, Dominik Lubeley
Life of this patent
Estimating the term…
Abstract
A method for generating a netlist of an FPGA program. The model of the FPGA program is composed of at least two components, each component being assigned a separate partition on the FPGA. An independent build is carried out for each component and an overall classification is generated from the components, wherein the build jobs are automatically started after a trigger event and the trigger event is a saving of a component, the exiting of a component of the design, or a time-controlled, automated initiation of a build.
Claims21
A method for generating a netlist of an FPGA program, an underlying model of the FPGA program being composed of at least two components, the method comprising:
- assigning each component a separate partition on the FPGA, wherein each component represents a logical circuit within an FPGA;
- performing an independent build of a netlist for each component, wherein the netlist represents wired interconnects between logical circuits in the FPGA;
- comparing a local classification of the netlist with versioned classifications of the components to determine if the versioned classifications are usable;
- generating an overall classification from the netlists of the components by incorporating the netlists directly into the overall classification;
- automatically starting the independent build after a trigger event, the trigger event being a saving of a component in a GUI, the exiting of a component of the model in the GUI, or a time-controlled, automated initiation of a build,
- wherein, if one of the versioned classifications is usable, then the versioned classification usable for a specific component of the at least two components is incorporated into the overall classification in place of the local classification or netlist, and
- generating a bit stream from the overall classification to configure a circuit configuration of the FPGA.
A method of building an FPGA circuit layout, comprising:
- pre-building at least two components of an FPGA program into at least two partial models;
- versioning each prebuilt component, wherein each component represents a logical circuit within an FPGA;
- determining if a prebuilt version exists as a previously versioned classification;
- if the prebuilt version was previously versioned, selecting the previously versioned classification for incorporation into a final build;
- if the prebuilt version was not previously versioned, selecting the prebuilt component for incorporation into the final build;
- generating at least one netlist for the partial models, wherein each netlist represents a wired interconnect between logical circuits in the FPGA;
- generating an overall classification from each netlist of each component or the previously versioned classification of each component;
- and
- generating a bit stream from the overall classification to configure a for circuit configuration of the FPGA.
Dependencies are inferred from the claim text.