Hardware processors and methods for tightly-coupled heterogeneous computing

A hardware processor comprising:

• a hardware decoder to decode an instruction into a decoded instruction;
• a hardware execution unit to execute the decoded instruction to:
• connect inputs of a plurality of execution units in parallel of the hardware processor to an output of a first buffer and outputs of a plurality of memory banks, and connecting inputs of the plurality of memory banks and parallel inputs of a plurality of second buffers to an output of the first buffer, outputs of the plurality of memory banks, and outputs of the plurality of execution units based on a control signal;
• and
• provide data to inputs of an offload engine from outputs of the plurality of second buffers.