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US 9,870,338 B2Granted
Systems, apparatuses, and methods for performing vector packed compression and repeat
AssigneeIntel Corporation
InventorsElmoustapha Ould-Ahmed-Vall, Thomas Willhalm
Life of this patent
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Abstract
Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed compression and repeat in response to a single vector packed compression and repeat instruction that includes a first and second source vector register operand, a destination vector register operand, and an opcode are described.
Claims20
A method comprising:
- decoding an instruction;
- executing the decoded instruction to determine, for each packed data element position of a first source vector register, a number of times that packed data element position's packed data element is to be stored in a destination vector register based solely on the value of a corresponding packed data element position of a second source vector register, wherein the number of times is up to a plurality of times and store each packed data element of a packed data element position of the first source vector register into the destination vector register the value number of times based on the determination of the corresponding data element of the second source vector register's value.
An article of manufacture comprising:
- a non-transitory machine-readable storage medium having stored thereon an occurrence of an instruction, wherein the instruction's format specifies as its source operands a first and second vector register and specifies as its destination a single vector register, and wherein the instruction format includes an opcode which instructs a machine, responsive to the single occurrence of the single instruction, to cause a determination, for each packed data element position of the first source vector register, a number of times that packed data element position's packed data element is to be stored in the destination vector register based solely on the value of a corresponding packed data element position of the second source vector register, storage of each packed data element of a packed data element position of the first source vector register into the destination vector register the value number of times based on the determination of the corresponding data element of the second source vector register's value, wherein the number of times is up to a plurality of times.
An apparatus comprising:
- a hardware decoder to decode a single instruction that includes a first and second source vector register operand, a destination vector register operand, and an opcode;
- execution circuitry to execute the decoded single instruction to determine, for each packed data element position of the first source vector register, a number of times that packed data element position's packed data element is to be stored in the destination vector register based solely on the value of a corresponding packed data element position of the second source vector register and store each packed data element of a packed data element position of the first source vector register into the destination vector register the value number of times based on the determination of the corresponding data element of the second source vector register's value, wherein the number of times is up to a plurality of times.
Dependencies are inferred from the claim text.