Techniques for escalating interrupts in a data processing system

A processing unit for a multithreaded data processing system, the processing unit comprising:

• an interrupt source controller (ISC);
• and
• an interrupt presentation controller (IPC) coupled to the ISC, wherein the IPC is configured to:
• receive an event notification message (ENM) from the ISC, wherein the ENM specifies a level, an event target number, and a number of bits to ignore;
• determine a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, and a process identifier (ID) when the level specified in the ENM corresponds to a user level, wherein the event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted;
• and
• in response to no virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, transmit an escalate message, wherein the escalate message includes an escalate event number that is used by the ISC to generate a subsequent ENM, and wherein the number of bits to ignore is ‘n’ bits and the specific virtual processor thread and (2n−1) other virtual processor threads may be potentially interrupted.

A design structure tangibly embodied in a computer-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• an interrupt source controller (ISC);
• and
• an interrupt presentation controller (IPC) coupled to the ISC, wherein the IPC is configured to:
• receive an event notification message (ENM) from the ISC, wherein the ENM specifies a level, an event target number, and a number of bits to ignore;
• and
• determine a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, and a process identifier (ID) when the level specified in the ENM corresponds to a user level, wherein the event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted;
• and
• in response to no virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, transmit an escalate message, wherein the escalate message includes an escalate event number that is used by an interrupt source controller (ISC) to generate a subsequent ENM, and wherein the number of bits to ignore is ‘n’ bits and the specific virtual processor thread and (2n−1) other virtual processor threads may be potentially interrupted.