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US 9,870,325 B2Granted
Common die implementation for memory devices with independent interface paths
AssigneeIntel Corporation
InventorKuljit S Bains
Life of this patent
Estimating the term…
Abstract
A memory device includes at least two independent interface paths, an interface path including multiple memory banks. The memory device can selectively operate in a bank mode or a bank group mode. In bank mode, banks are operated as logical banks, where separate physical banks from different interface paths operate in parallel. When a logic bank is accessed, all physical banks belonging to the logical bank are accessed in parallel across the interface paths. In bank group mode, banks are operated independently, but accessed in bank groups. A separate interface path is operated as an independent bank group, and a bank is individually accessed in its bank group. In bank group mode, back to back access to separate bank groups is possible without resulting in access delay.
Claims22
A memory device to interface in a memory subsystem, comprising:
- input/output (I/O) interface hardware with a bandwidth to couple to a data bus;
- a memory array including a first bank group having multiple memory banks and a second bank group having multiple memory banks;
- and
- circuitry in the memory device to selectively couple the memory banks of the first bank group and the memory banks of the second bank group to the I/O interface hardware in bank mode or in bank group mode,
- wherein in bank mode, at least one bank of the first bank group and at least one bank of the second bank group are accessed in parallel as a logical bank, wherein the at least one bank of the first bank group and the at least one bank of the second bank group are accessed in parallel in response to a command with a bank address identifier and without a bank group identifier, wherein in bank mode the bandwidth is a full I/O bandwidth available in the I/O interface hardware;
- and
- wherein in bank group mode, the banks of the first bank group are accessed independently of the banks of the second bank group, in response to a command with a bank address identifier and a bank group identifier, wherein in bank group mode the bandwidth is only a portion of the full I/O bandwidth available in the I/O interface hardware.
4 more elements
A method for interfacing in a memory subsystem, comprising:
- generating a memory access command to a memory device having an input/output (I/O) interface hardware with a bandwidth to couple to a data bus, and a memory array including a first bank group having multiple memory banks and a second bank group having multiple memory banks;
- and
- sending the memory access command to the memory device to cause the memory device to operate on the memory access command differently, depending on whether the memory device is selectively configured for bank mode or bank group mode,
- wherein in bank mode, at least one bank of the first bank group and at least one bank of the second bank group are accessed in parallel as a logical bank, wherein the at least one bank of the first bank group and the at least one bank of the second bank group are accessed in parallel in response to a command with a bank address identifier and without a bank group identifier, wherein in bank mode the bandwidth is a full I/O bandwidth available in the I/O interface hardware;
- and
- wherein in bank group mode, the banks of the first bank group are accessed independently of the banks of the second bank group, in response to a command with a bank address identifier and a bank group identifier, wherein in bank group mode the bandwidth is only a portion of the full I/O bandwidth available in the I/O interface hardware.
3 more elements
An electronic device with a memory subsystem, comprising:
- at least one processor;
- a memory controller;
- a network interface, the at least one processor communicatively coupled to the memory controller and the network interface communicatively coupled to the at least one processor;
- a memory device coupled to the memory controller, the memory device including
- input/output (I/O) interface hardware with a bandwidth to couple to a data bus;
- a memory array including a first bank group having multiple memory banks and a second bank group having multiple memory banks;
- and
- circuitry in the memory device to selectively couple the memory banks of the first bank group and the memory banks of the second bank group to the I/O interface hardware in bank mode or in bank group mode,
- wherein in bank mode, at least one bank of the first bank group and at least one bank of the second bank group are accessed in parallel as a logical bank, wherein the at least one bank of the first bank group and the at least one bank of the second bank group are accessed in parallel in response to a command with a bank address identifier and without a bank group identifier, wherein in bank mode the bandwidth is a full I/O bandwidth available in the I/O interface hardware;
- and
- wherein in bank group mode, the banks of the first bank group are accessed independently of the banks of the second bank group, in response to a command with a bank address identifier and a bank group identifier, wherein in bank group mode the bandwidth is only a portion of the full I/O bandwidth available in the I/O interface hardware;
- and
- a touchscreen display coupled to generate a display based on data accessed from the memory device.
10 more elements
Dependencies are inferred from the claim text.