Logic circuit for the gathering of trace data

A method for collecting trace data from a plurality of functional logic units in a logic circuit, each functional logic unit having an independent clock signal and a trace bus for carrying trace data, wherein each trace bus is comprised of at least two parallel portions and the corresponding trace data is apportioned among the at least two portions of trace data, the method comprising:

• providing a trace gathering logic unit for simultaneously collecting trace data from the functional logic units, the trace gathering logic unit having a clock signal independent of clock signals of the functional logic units and a trace bus for receiving trace data from the functional logic units;
• multiplexing the at least two portions of trace data from different functional logic units onto the trace bus of the trace gathering logic unit via multiplexing logic;
• communicating, via synchronization logic coupled to the multiplexing logic, trace data from the functional logic units to the trace gathering logic unit based on the clock signal of the trace gathering logic unit;
• determining, via detection logic of the synchronization logic, when valid trace data from the functional logic units is available for placing on the trace bus of the trace gathering logic unit;
• and,
• signalling to the trace gathering logic unit, via signalling logic of the synchronization logic, which signalling logic is coupled to the detection logic, that valid trace data is on the trace bus.

A computer programming product for collecting trace data from a plurality of functional logic units in a logic circuit, each functional logic unit having an independent clock signal and a trace bus for carrying trace data, wherein each trace bus is comprised of at least two parallel portions and the corresponding trace data is apportioned among the at least two portions of trace data, the method comprising:

• a processor,
• a non-transitory memory coupled to the processor;
• and
• logic, stored on the memory for execution on the processor for:
• providing a trace gathering logic unit for simultaneously collecting trace data from the functional logic units, the trace gathering logic unit having a clock signal independent of clock signals of the functional logic units and a trace bus for receiving trace data from the functional logic units;
• multiplexing the at least two portions of trace data from different functional logic units onto the trace bus of the trace gathering logic unit via multiplexing logic;
• communicating, via synchronization logic coupled to the multiplexing logic, trace data from the functional logic units to the trace gathering logic unit based on the clock signal of the trace gathering logic unit;
• determining, via detection logic of the synchronization logic, when valid trace data from the functional logic units is available for placing on the trace bus of the trace gathering logic unit;
• and,
• signalling to the trace gathering logic unit, via signalling logic of the synchronization logic, which signalling logic is coupled to the detection logic, that valid trace data is on the trace bus.