Memory device performing post package repair (PPR) operation
AssigneeSamsung Electronics Co., Ltd.
InventorsSeong-Jin Lee, Ju-Yun Jung, Yoo-Jung Lee
Life of this patent
Estimating the term…
Abstract
A memory device including; a memory cell array including memory cells connected to word lines and bit lines, and redundancy memory cells connected to a redundancy word line and the bit lines, and control logic configured to control execution of a post package repair operation by the memory device. The control logic includes a PPR control circuit that programs a bad row address to a non-volatile memory during a normal PPR operation in response to the normal PPR command, and programs the bad row address to a volatile memory during a fast PPR operation in response to the fast PPR command, and replaces the bad row in the memory cell array with a redundancy row associated with the redundancy word line.
Claims19
A memory device that receives from a memory controller a bad row address designating a bad row associated with a bad word line and one of a normal post package repair (PPR) command and a fast PPR (sPPR) command, the memory device comprising:
- a memory cell array including memory cells connected to word lines and bit lines, and redundancy memory cells connected to a redundancy word line and the bit lines;
- and
- a control logic configured to control execution of a PPR operation by the memory device,
- wherein the control logic comprises a PPR control circuit that programs the bad row address to a non-volatile memory during a normal PPR operation in response to the normal PPR command, and programs the bad row address to a volatile memory during a fast PPR operation in response to the fast PPR command, and replaces the bad row in the memory cell array with a redundancy row associated with the redundancy word line.
A memory device that receives from a memory controller a bad column address designating a bad column associated with a bad bit line and one of a normal post package repair (PPR) command and a fast PPR (sPPR) command, the memory device comprising:
- a memory cell array including memory cells connected to word lines and bit lines, and redundancy memory cells connected to a redundancy bit line and the word lines;
- and
- a control logic configured to control execution of a PPR operation by the memory device,
- wherein the control logic comprises a PPR control circuit that programs the bad column address to a non-volatile memory during a normal PPR operation in response to the normal PPR command, and programs the bad column address to a volatile memory during a fast PPR operation in response to the fast PPR command, and replaces the bad column in the memory cell array with a redundancy column associated with the redundancy bit line.
A method of operating a memory device which includes memory cells connected to word lines and bit lines, and redundancy memory cells connected to one of a redundancy bit line and a redundancy word line, the method comprising:
- entering a one of a normal post package repair (PPR) mode or a fast PPR mode in response to a received PPR command and a bad address, the bad address being one of:
- a bad column address designating a bad column and a bad row address designating a bad row;
- when in the normal PPR mode, storing the bad address to a non-volatile memory;
- when in the fast PPR mode, storing the bad address to a volatile memory;
- when the bad address is the bad column address, replacing the bad column in the memory cell array with a redundancy column associated with the redundancy bit line;
- when the bad address is the bad row address, replacing the bad row in the memory cell array with a redundancy row associated with the redundancy word line;
- and
- writing data to the redundancy memory cells replacing memory cells selected by the bad address.
Dependencies are inferred from the claim text.