Memory error detection
AssigneeRambus Inc.
InventorsIan Shaeffer, Craig E. Hampel
Life of this patent
Estimating the term…
Abstract
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation
Claims20
A memory controller integrated circuit, comprising:
- circuitry to transmit, to a memory device, an address with a write command that specifies a write operation;
- circuitry to receive from the memory device error detection information dependent on the address received by the memory device;
- circuitry to determine from the error detection information whether there is an error in the address received by the memory device;
- and
- circuitry to transmit a signal to the memory device dependent on whether or not there is detected error in the address received by the memory device, as determined from the error detection information, wherein the memory device is to execute the write command dependent on whether or not it has received the signal.
A memory controller integrated circuit, comprising:
- circuitry to transmit, to a memory device, an address with a write command that specifies a write operation;
- circuitry to receive from the memory device error detection information dependent on the address received by the memory device;
- circuitry to determine from the error detection information whether there is an error in the address received by the memory device;
- circuitry to, in the event of detected error in the address received by the memory device, transmit to the memory device a signal to cause the memory device to abort execution of the write command;
- and
- a buffer that is to hold information representing the address, and wherein the circuitry to determine is to determine whether the error detection information represents error relative to the information held in the buffer.
A memory controller integrated circuit, comprising:
- circuitry to transmit, to a memory device, an address with a write command that specifies a write operation;
- circuitry to receive from the memory device error detection information dependent on the address received by the memory device;
- circuitry to determine from the error detection information whether there is an error in the address received by the memory device;
- and
- circuitry to, in the event of detected error in the address received by the memory device, transmit to the memory device a signal for the memory device to execute the write command if the memory controller has determined from the error detection information that there is no error in the write command, to cause the write of data corresponding to the write command into memory.
Dependencies are inferred from the claim text.