Performing stencil computations
AssigneeThe Regents of the University of California
InventorDavid Donofrio
Life of this patent
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Abstract
A method and apparatus for performing stencil computations efficiently are disclosed. In one embodiment, a processor receives an offset, and in response, retrieves a value from a memory via a single instruction, where the retrieving comprises: identifying, based on the offset, one of a plurality of registers of the processor; loading an address stored in the identified register; and retrieving from the memory the value at the address.
Claims20
A method comprising:
- receiving, by a processor, an offset from a cell of a multidimensional grid, wherein the offset corresponds to an index of one of a plurality of registers of the processor;
- and
- retrieving by the processor, via a single instruction, a value from a memory address associated with the offset in response to the receiving of the offset, wherein the retrieving comprises:
- identifying, based on the offset, the one of the plurality of registers of the processor, wherein the identified register corresponds to a dimension and a polarity of the multidimensional grid;
- loading the memory address stored in the identified register;
- and
- retrieving the value from the memory address.
A non-transitory computer readable storage medium including instructions that, when executed by a processor, cause the processor to perform operations comprising:
- predetermining, by the processor, a first address of a memory based on:
- a second address of the memory corresponding to a cell of a multidimensional grid, a first stride value for a first dimension of the multidimensional grid, and a first polarity;
- storing, by the processor, the first address in a first register of the processor that is associated with the first dimension and with the first polarity;
- predetermining, by the processor, a third address of the memory based on:
- the second address, a second stride value for a second dimension of the multidimensional grid, and a second polarity;
- and
- storing, by the processor, the third address in a second register of the processor that is associated with the second dimension and with the second polarity.
A system comprising:
- a plurality of registers to store data;
- an arithmetic logic unit (ALU);
- and
- a coprocessor to:
- receive from the ALU an offset from a cell of a multidimensional grid wherein the offset corresponds to an index of one of a plurality of registers of the coprocessor, and
- retrieve a value from a memory address associated with the offset via a single instruction, wherein to retrieve the value from memory via a single instruction the coprocessor is further to:
- identify, based on the offset, the one of the plurality of registers of the coprocessor, wherein the identified register is associated with a dimension and a polarity of the multidimensional grid;
- load the memory address stored in the identified register;
- and
- retrieve the value from the memory address.
Dependencies are inferred from the claim text.