Instruction and logic for reducing data cache evictions in an out-of-order processor
AssigneeIntel Corporation
InventorsJohn H. Kelm, Demos Pavlou, Mirem Hyuseinova
Life of this patent
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Abstract
A processor includes a resource scheduler, a dispatcher, and a memory execution unit. The memory execution unit includes logic to identify an executed, unretired store operation in a memory ordered buffer, determine that the store operation is speculative, determine whether an associated cache line in a data cache is non-speculative, and determine whether to block a write of the store operation results to the data cache based upon the determination that the store operation is speculative and a determination that the associated cache line is non-speculative.
Claims20
A processor, comprising:
- a resource scheduler including circuitry to assign alias resources to instructions within an atomic region of instructions, the atomic region including a plurality of reordered instructions;
- and
- a memory execution unit including circuitry to:
- identify an executed, unretired store operation from the atomic region in a memory ordered buffer;
- determine that the store operation is speculative, wherein a speculative store operation is a store operation having a potential to cause a data-dependency violation;
- determine that a particular cache line in a data cache associated with the store operation is non-speculative based on the particular cache line comprising result data of one or more non-speculative operations;
- and
- determine that a write of a result of the store operation to the data cache is to be blocked, at least temporarily, based upon the determination that the store operation is speculative and a determination that the particular cache line is non-speculative.
A method comprising, within a processor:
- dispatching an atomic region of instructions for execution;
- identifying an executed, unretired store operation within the atomic region in a memory ordered buffer;
- determining that the store operation is speculative, wherein a speculative store operation is a store operation having a potential to cause a data-dependency violation;
- determining that a particular cache line in a data cache associated with the store operation is non-speculative based on the particular cache line comprising result data of one or more non-speculative operations;
- and
- determining that a write of a result of the store operation to the data cache is to be blocked, at least temporarily, based upon the determination that the store operation is speculative and a determination that the particular cache line is non-speculative.
A system comprising a processor, the processor including:
- a resource scheduler including circuitry to assign alias resources to instructions within an atomic region of instructions, the atomic region including a plurality of reordered instructions;
- and
- a memory execution unit including circuitry to:
- identify an executed, unretired store operation in the atomic region in a memory ordered buffer;
- determine that the store operation is speculative, wherein a speculative store operation is a store operation having a potential to cause a data-dependency violation;
- determine that a particular cache line in a data cache associated with the store operation is non-speculative based on the particular cache line comprising result data of one or more non-speculative operations;
- and
- determine that a write of a result of the store operation to the data cache is to be blocked, at least temporarily, based upon the determination that the store operation is speculative and a determination that the particular cache line is non-speculative.
Dependencies are inferred from the claim text.