Control chip memory power sequence
AssigneeNuvoton Technology Corporation
InventorsHsin-Lung Yang, Ming-Che Hung
Life of this patent
Estimating the term…
Abstract
A control chip for memory power sequence including input pins, a control circuit and output pins is provided. The control chip is compatible with a plurality of processor platforms. The input pins are configured to receive control signals corresponding to each of the processor platforms. The control circuit is configured to determine a selected processor platform among the processor platforms in which the control chip for memory power sequence is operated, and generate corresponding power switching signals according to the control signals of the selected processor platform. The output pins are configured to output the corresponding power switching signals to control a power sequence of a memory on the selected processor platform.
Claims10
A control chip for memory power sequence compatible with a plurality of processor platforms, the control chip comprising:
- a plurality of input pins, configured to receive a plurality of control signals corresponding to each of the processor platforms;
- a platform selection circuit, configured to provide at least one selection signal instructing the control chip for memory power sequence to be operated in a selected processor platform among the plurality of processor platforms;
- a plurality of power sequence circuits, each of the power sequence circuits being configured to generate a plurality of power switching signals of one of the processor platforms according to the control signals;
- an input selection circuit, coupled to the input pins to receive the control signals, coupled to the platform selection circuit to receive the at least one selection signal, and transmitting the control signals to one of the power sequence circuits according to the at least one selection signal;
- an output selection circuit, coupled to the platform selection circuit to receive the at least one selection signal, coupled to the power sequence circuits to receive the power switching signals of each of the power sequence circuits, and selecting the power switching signals of said one of the power sequence circuits according to the at least one selection signal;
- and
- a plurality of output pins, coupled to the output selection circuit, and outputting the selected power switching signals to control a power sequence of a memory on the selected processor platform.
A control chip for memory power sequence compatible with an Intel processor platform and an AMD processor platform, the control chip for memory power sequence comprising:
- a first multi-function pin, configured to receive a SLP_S4# signal of a chip set of the Intel processor platform, or configured to receive a SLP_S5# signal of an application processor unit of the AMD processor platform;
- a second multi-function pin, configured to receive a VPP_PG signal of the Intel processor platform, or configured to receive an AM4R1 signal of the application processor unit of the AMD processor platform;
- a third function pin, configured to receive a SLP_S3# signal of the chip set of the Intel processor platform, or configured to receive a SLP_S3# signal of the application processor unit of the AMD processor platform;
- and
- a fourth multi-function pin, configured to receive a DDR_VTT_CNTL signal of a central processor unit of the Intel processor platform, or configured to receive a S0A3_GPIO signal of the application processor unit of the AMD processor platform;
- a control circuit, coupled to the first multi-function pin, the second multi-function pin, the third function pin and the fourth multi-function pin, wherein when the control circuit determines that the control chip for memory power sequence is operated in the Intel processor platform, the control circuit correspondingly generates a first power switching signal, a second power switching signal and a third power switching signal according to the SLP_S4# signal, the VPP_PG signal, the SLP_S3# signal and the DDR_VTT_CNTL signal, and when the control circuit determines that the control chip for memory power sequence is operated in the AMD processor platform, the control circuit correspondingly generates the first power switching signal, the second power switching signal and the third power switching signal according to the SLP_S5# signal, the AM4R1 signal, the SLP_S3# signal and the S0A3_GPIO signal;
- a fifth multi-function pin, coupled to the control circuit, and configured to output the first power switching signal to control a power sequence of a VPP power source of a DDR4 SDRAM circuit of the Intel processor platform or the AMD processor platform;
- a sixth multi-function pin, coupled to the control circuit, and configured to output the second power switching signal to control a power sequence of a VDD power source or a VDDQ power source of the DDR4 SDRAM circuit;
- and
- a seventh multi-function pin, coupled to the control circuit, and configured to output the third power switching signal to control a power sequence of a VTT power source of the DDR4 SDRAM circuit.
Dependencies are inferred from the claim text.