Apparatus and method for optimized n-write/1-read port memory design

A method to support write operations to an optimized design of n-write/1-read memory with buffered write requests, comprising:

• accepting a first write request Wr_0 directly from its write interface at a crossbar, which then writes data packet in the Wr_0 to one of the memory banks in a memory unit at a memory address specified in the Wr_0 during the current clock cycle;
• checking a current write request Wr_k, k>0 with each memory module in a set of k temporary memory modules coupled to the write interface of Wr_k to determine if it intends to write to the same memory bank as any one of higher prioritized write requests Wr_0 through Wr_(k−1) and thus causes a conflict;
• accepting Wr_k at the crossbar, which then writes data packet in the Wr_k to one of the memory banks at a memory address specified in the Wr_k during the current clock cycle if Wr_k is writing to a different memory bank from the write requests Wr_0 through Wr_(k−1);
• storing Wr_k in a corresponding memory module in the set of k temporary memory modules at the memory address specified in the Wr_k during the current clock cycle if Wr_k is writing to the same memory bank as one of the write requests Wr_0 through Wr_(k−1);
• retrieving and executing the Wr_k stored in the memory module to one of the memory banks at the memory address specified in the Wr_k during a later clock cycle when there is no conflict between Wrk and Wr_0 through Wr_(k−1).