Address collision avoidance in a memory device
AssigneeAvago Technologies General IP (Singapore) Pte. Ltd.
InventorsRobert E. Ward, Brian Lessard
Life of this patent
Estimating the term…
Abstract
Embodiments herein provide for avoiding address collisions in a memory device. In one embodiment, a memory controller includes a command scheduler operable to process a read-modify-write I/O command to a location in memory, to detect another I/O command to the same memory location while the read-modify-write I/O command is accessing the memory location, and to stall the other I/O command until the read-modify-write I/O command is complete while allowing a third I/O command to access the memory.
Claims20
A memory controller, comprising:
- a command scheduler operable to process a first read-modify-write Input/Output (I/O) command to a memory location, to detect another I/O command to the same memory location while the first read-modify-write I/O command is accessing the memory location, to extract and track a memory address from the another I/O command if the another I/O command is a read-modify-write I/O command and to not extract and not track the memory address from the another I/O command if the another I/O command is not a read-modify-write command, and to stall the another I/O command until the first read-modify-write I/O command is complete while allowing a third I/O command to access the memory.
A method operable in a memory controller, the method comprising:
- modifying data at a first location in memory with a first read-modify-write Input/Output (I/O) command;
- detecting a second I/O command to the first location in the memory while the first read-modify-write command is modifying the data;
- extracting and tracking a memory address from the second I/O command if the second I/O command is a read-modify-write I/O command and not extracting and not tracking the memory address from the second I/O command if the second I/O command is not a read-modify-write I/O command;
- stalling the second I/O command until the first read-modify-write I/O command is complete;
- detecting a third I/O command to a second different location in the memory while the first read-modify-write I/O command is modifying the data;
- and
- allowing the third I/O command to access the second location in the memory while the first read-modify-write I/O command is modifying the data.
A non-transitory computer readable medium comprising instructions that, when executed by a memory controller, direct the memory controller to:
- modify data at a first location in memory with a first read-modify-write Input/Output (I/O) command;
- detect a second I/O command to the first location in the memory while the first read-modify-write command is modifying the data;
- extract and track a memory address from the second I/O command if the second I/O command is a read-modify-write I/O command and not extract and not track of the memory address from the second I/O command if the second I/O command is not a read-modify-write I/O command;
- stall the second I/O command until the first read-modify-write I/O command is complete;
- detect a third I/O command to a second different location in the memory while first the read-modify-write I/O command is modifying the data;
- and
- allow the third I/O command to access the second location in the memory while the first read-modify-write I/O command is modifying the data.
Dependencies are inferred from the claim text.