US 9,870,169 B2 · Interleaved all-level programming of non-volatile memory

Abstract

Techniques are disclosed for programming memory devices such as solid-state drives. In an embodiment, a memory controller is configured to execute a programming sequence that interleaves coarse and fine tuning steps for neighboring word lines. In one example, three consecutive word lines are programmed in six steps. At step 1, word line n is coarse programmed to an intermediate voltage level; at step 2, word line n+1 is coarse programmed to an intermediate voltage level; at step 3, word line n is fine programmed to its target voltage level; at step 4, word line n+2 is coarse programmed to an intermediate voltage level; at step 5, word line n+1 is fine programmed to its target voltage level; at step 6, word line n+2 is fine programmed to its target voltage level. No reads are allowed until all cell levels are programmed. Phase change memory may be used as staging buffer.

Claims25

Dependent claims

A method for programming a non-volatile memory device having a plurality of word lines each operatively coupled to a plurality of multi-level storage cells, the method comprising:

programming word line n to an intermediate voltage level;
programming word line n+1 to an intermediate voltage level;
programming word line n to its target voltage level;
programming word line n+2 to an intermediate voltage level;
programming word line n+1 to its target voltage level;
programming word line n+2 to its target voltage level;
and
suppressing reads to word line n, word line n+1, and word line n+2, until each of word line n, word line n+1, and word line n+2 is programmed to its target voltage level.

5 more elements

A solid-state storage system, comprising:

a host interface configured to receive data for storage;
a phase change memory with switch (PCMS) configured to stage data received by the host interface;
a PCMS controller configured to facilitate the writing of data to the PCMS;
NAND flash memory configured to store data staged in the PCMS and having a plurality of word lines each operatively coupled to a plurality of storage cells;
a NAND controller configured to facilitate the writing of data to the NAND flash memory;
a processor configured to facilitate movement of staged data from the PCMS to the NAND flash memory, wherein processor is configured to
program word line n to an intermediate voltage level,
program word line n+1 to an intermediate voltage level,
program word line n to its target voltage level,
program word line n+2 to an intermediate voltage level,
program word line n+1 to its target voltage level,
program word line n+2 to its target voltage level, and
suppress reads to word line n, word line n+1, and word line n+2 until each of word line n, word line n+1, and word line n+2 is programmed to its target voltage level.

10 more elements

Dependencies are inferred from the claim text.

Interleaved all-level programming of non-volatile memory

Life of this patent

Interleaved all-level programming of non-volatile memory

Life of this patent

Abstract

Claims25