Double bandwidth algorithmic memory array
AssigneeGlobalfoundries Inc.
InventorsIgor Arsovski, Eric D. Hunt-Schroeder, Mark W. Kuemerle
Life of this patent
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Abstract
The present disclosure relates to memory structures and, more particularly, to double bandwidth algorithmic memory array structures and methods of use. The memory array includes: a plurality of memory banks each of which includes addressable storage units; a redundant array of independent disks (RAID) bank which stores parity bits corresponding to data written into any of the plurality of memory banks at a same address; and a plurality of XOR gates in which data written into any of the plurality of memory banks is cascaded therethrough to refresh the parity bits in the RAID bank.
Claims20
A memory array, comprising:
- a plurality of memory banks each of which includes addressable storage units;
- a redundant array of independent disks (RAID) bank which stores parity bits corresponding to data written into any of the plurality of memory banks at a same address;
- and
- a plurality of XOR gates in which data written into any of the plurality of memory banks is cascaded therethrough to refresh the parity bits in the RAID bank.
A memory array, comprising:
- a plurality of memory banks each of which includes addressable storage units;
- a write buffer;
- a plurality of XOR gates in which data written into any of the plurality of memory banks is cascaded therethrough to the write buffer;
- and
- an additional memory bank which stores parity bits corresponding to data written into any of the plurality of memory banks at a same address in subsequent write cycles, as received from the write buffer during a write operation.
A method, comprising:
- writing data into a memory bank of a plurality of memory banks;
- cascading the write data of the memory bank and read data of other memory banks of the plurality of memory banks through a plurality of XOR gates;
- storing the write data for the memory bank as a parity bit in a write buffer;
- and
- refreshing another memory bank with a previous parity bit stored in the write buffer from a previous write operation performed on the memory bank or another memory bank.
Dependencies are inferred from the claim text.