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US 9,870,156 B2Granted
Memory system and method of controlling memory system
AssigneeToshiba Memory Corporation
InventorYuki Nagata
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a memory system is provided wherein an interruption generating unit generates an interruption signal for one or more commands executed by a transfer executing unit when an end number counter is greater than or equal to a first threshold. A transfer type conjecturing unit determines whether the transfer type of a first command to be executed after transmitting the interruption signal is sequential transfer or random transfer and sets the first threshold at a value different between when determining being the sequential transfer and when determining being the random transfer.
Claims20
A memory system comprising:
- a nonvolatile storage memory;
- a command receiving circuit that receives commands from a host;
- a command transmitting circuit that transmits an interruption signal upon the execution of the commands to the host;
- a command queue that queues the commands;
- a transfer executing circuit that executes the commands queued in the command queue sequentially to write data into the nonvolatile storage memory or to read data from the nonvolatile storage memory;
- an end number counter that, after transmitting the interruption signal to the host, counts the number of commands that the transfer executing circuit has finished executing;
- an interruption generating circuit that generates an interruption signal for the commands executed by the transfer executing circuit, the number of the commands being one or greater, when the end number counter is greater than or equal to a first threshold;
- and
- a transfer type conjecturing circuit that determines whether the transfer type of a first command to be first executed after transmitting the interruption signal, which is queued in the command queue, is sequential transfer or random transfer and sets the first threshold at a smaller value when determining that the transfer type is the random transfer than when determining that the transfer type is the sequential transfer.
6 more elements
A memory system comprising:
- a nonvolatile storage-memory;
- a command receiving circuit that receives commands from a host;
- a command transmitting circuit that transmits an interruption signal upon the execution of the commands to the host;
- a command history information storing circuit that stores history information about commands received in the past;
- a transfer executing circuit that executes the commands received to write data into the nonvolatile storage memory or to read data from the nonvolatile storage memory;
- an end number counter that, after transmitting the interruption signal to the host, counts the number of commands that the transfer executing circuit has finished executing;
- an interruption generating circuit that generates an interruption signal for the commands executed by the transfer executing circuit, the number of the commands being one or greater, when the end number counter is greater than or equal to a first threshold;
- and
- a transfer type conjecturing circuit that determines whether the transfer type of each of the commands received by the command receiving circuit is sequential transfer or random transfer based on the history information stored in the command history information storing circuit and sets the first threshold at a smaller value when determining that the transfer type is the random transfer than when determining that the transfer type is the sequential transfer.
6 more elements
A memory system comprising:
- a nonvolatile memory;
- and
- a controller circuit configured to queue commands received from a host device and to generate an interruption signal, the interruption signal indicating to the host device that the memory system executes at least one command among the queued commands, wherein
- the controller circuit generates a first interruption signal for a first command, execute a second command and after a first interval, generates a second interruption signal for the second command, and
- the first interval in a case where the second command requests a random transfer with respect to the first command is shorter than in a case where the second command requests a sequential transfer with respect to the first command.
2 more elements
Dependencies are inferred from the claim text.